SNLS323N August   2010  – January 2017 LMH0395

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Switching Characteristics for SPI Interface
    8. 6.8 Timing Requirements for SPI Interface
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Mute Reference (MuteREF)
      2. 7.3.2 Carrier Detect (CD) and Mute
      3. 7.3.3 Input Interfacing
      4. 7.3.4 Output Interfacing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto Sleep
    5. 7.5 Programming
      1. 7.5.1 SPI Register Access
        1. 7.5.1.1  SPI Transaction Overview
        2. 7.5.1.2  SPI Write
        3. 7.5.1.3  SPI Read
        4. 7.5.1.4  SPI Daisy-Chain Operation
        5. 7.5.1.5  SPI Daisy-Chain Write
        6. 7.5.1.6  SPI Daisy-Chain Read
        7. 7.5.1.7  SPI Daisy-Chain Read and Write Example
        8. 7.5.1.8  SPI Daisy-Chain Length Detection
        9. 7.5.1.9  Output Driver Adjustments and De-Emphasis Setting
        10. 7.5.1.10 Launch Amplitude Optimization
        11. 7.5.1.11 Cable Length Indicator (CLI)
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Interfacing to 3.3-V SPI
      2. 8.1.2 Crosstalk Immunity
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Dos and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMH0395 3 Gbps HD/SD Dual Output SDI Low Power Extended Reach Adaptive Cable Equalizer is designed to equalize data transmitted over cable (or any media with similar dispersive loss characteristics). The equalizer operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, ST 259, and DVB-ASI standards. Additional features include separate carrier detect and output mute pins which may be tied together to mute the output when no signal is present. A programmable mute reference is provided to mute the output at a selectable level of signal degradation. The bypass pin allows the adaptive equalizer to be bypassed. The LMH0395 accepts single-ended input. The input must be AC coupled. The LMH0395 correctly handles equalizer pathological signals for standard definition and high definition serial digital video, as described in ST RP 178 and RP 198, respectively.

8.1.1 Interfacing to 3.3-V SPI

The LMH0395 may be controlled through optional SPI register access. The LMH0395 SPI pins support 2.5-V LVCMOS logic levels and are compliant with JEDEC JESD8-5 (see DC Electrical Characteristics). Care must be taken when interfacing the SPI pins to other voltage levels.

The 2.5-V LMH0395 SPI pins may be interfaced to a 3.3-V compliant SPI host by using a voltage divider or level translator. One implementation is a simple resistive voltage divider as shown in Figure 15.

LMH0395 30115730.gif Figure 15. 3.3-V SPI Interfacing

8.1.2 Crosstalk Immunity

Single-ended SDI signals are susceptible to crosstalk and good design practices should be employed to minimize its effects. Most crosstalk originates through capacitive coupling from adjacent signals routed closely together through traces and connectors. To reduce capacitive coupling, SDI signals should be appropriately spaced apart or insulated from one another. This can be accomplished by physically isolating signal traces in the layout and by providing additional ground pins between signal traces in connectors as necessary. These techniques help to reduce crosstalk but do not eliminate it.

The LMH0395 was designed specifically with crosstalk in mind and incorporates advanced circuit design techniques that help to isolate and minimize the effects of cross-coupling in high-density system designs.The LMH0395's enhanced design results in minimal degradation in cable reach in the presence of crosstalk and overall superior immunity against cross-coupling from neighboring channels.

8.2 Typical Application

Figure 16 shows the application circuit for the LMH0395 in SPI mode. (Note: The application circuit shows an external capacitor connected between the AEC+ and AEC- pins as commonly configured in legacy equalizers. This capacitor is optional and not necessary for the LMH0395; the AEC+ and AEC- pins may be left unconnected with no change in performance.)

LMH0395 30115717.gif Figure 16. Application Circuit (SPI Mode)

8.2.1 Design Requirements

Table 2 lists the design parameters of the LMH0395.

Table 2. LMH0395 Design Parameters

DESIGN PARAMETERS REQUIREMENTS
Input AC coupling capacitors Required. A common type of AC coupling capacitor is 1 µF ± 10% X7R ceramic capacitor (0402 or 0201 size).
Distance from Device to BNC Keep this distance as short as possible to minimize parasitic
High Speed SDI, and SDI, trace impedance Design single-ended trace impedance with 75 Ω ± 5%
High Speed SDO0, SDO0, SDO1, and SDO1 trace impedance Design differential trace impedance with 100 Ω ± 5%
DC Power Supply Coupling Capacitors To minimize power supply noise, use 0.1-µF capacitors as close to the device VDD pin as possible

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

  1. Maximum power draw for PCB regulator selection: Use maximum current consumption in the data sheet to compute maximum power consumption.
  2. Closely compare schematic against typical connection diagram in the data sheet.
  3. Plan out the PCB layout and component placement to minimize parasitic.
  4. Consult the BNC vendor for optimum BNC landing pattern.

8.2.3 Application Curves

LMH0395 1.485_Gbps_200m_curve.gif
Figure 17. Differential Serial Data Output After Equalizing 200 Meters of Belden 1694A at 1.485 Gbps, PRBS10
LMH0395 Signal_after_20-30_FR4_curve.gif
Figure 19. Differential Serial Data Output 2.97 Gbps PRBS10 After 20” FR4 and 0 dB De-Emphasis
LMH0395 270_Mbps_200m_curve.gif
Figure 18. Differential Serial Data Output After Equalizing 200 Meters of Belden 1694A at 270 Mbps, PRBS10
LMH0395 Signal_after_20-30_FR4_5dB_de-emphasis_cuvre.gif
Figure 20. Differential Serial Data Output 2.97 Gbps PRBS10 After 20” FR4 and 5dB De-Emphasis

8.3 Dos and Don'ts

Special attention should be paid to the PCB layout for the high speed signals. SMPTE specifies the requirements for the Serial Digital Interface to transport digital video at SD, HD, and 3 Gbps data rates over coaxial cables. One of the requirements is meeting the required Return Loss. This requirement specifies how closely the port resembles 75-Ω impedance across a specified frequency band. The SMPTE specifications also defines the use of AC coupling capacitors for transporting uncompressed serial data streams with heavy low frequency content. This specification requires the use of a 1-µF AC coupling capacitor on the input of the LMH0395 to avoid low frequency bandwidth limitation.