SNVS178H January   2002  – December 2015 LM3485

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hysteretic Control Circuit
      2. 7.3.2 Current Limit Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start Up
      2. 7.4.2 External Sense Resistor
      3. 7.4.3 PGATE
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Step by Step Design Procedure
        2. 8.2.2.2 Inductor Selection (L1)
        3. 8.2.2.3 Output Voltage Set Point
        4. 8.2.2.4 Output Capacitor Selection (COUT)
        5. 8.2.2.5 Input Capacitor Selection (CIN)
        6. 8.2.2.6 Programming the Current Limit (RADJ)
        7. 8.2.2.7 Catch Diode Selection (D1)
        8. 8.2.2.8 P-Channel MOSFET Selection (Q1)
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DGK Package
8-Pin VSSOP
Top View
LM3485 20034609.png

Pin Functions

NO. NAME I/O DESCRIPTION
1 ISENSE I The current sense input pin. This pin should be connected to Drain node of the external PFET.
2 GND G Signal ground
3 NC — No connection
4 FB I The feedback input. Connect the FB to a resistor voltage divider between the output and GND for an adjustable output voltage.
5 ADJ I Current limit threshold adjustment. It connects to an internal 5.5-µA current source. A resistor is connected between this pin and the input Power Supply. The voltage across this resistor is compared with the VDS of the external PFET to determine if an over-current condition has occurred.
6 PWR GND G Power ground
7 PGATE O Gate Drive output for the external PFET. PGATE swings between VIN and VIN-5 V.
8 VIN P/I Power supply input pin