10.1 Layout Guidelines

The PC board layout is very important in all switching regulator designs. Poor layout can cause switching noise into the feedback signal and general EMI problems. For minimal inductance, the wires indicated by heavy lines should be as wide and short as possible. Keep the ground pin of the input capacitor as close as possible to the anode of the diode. This path carries a large AC current. The switching node, the node with the diode cathode, inductor, and FET drain, should be kept short. This node is one of the main sources for radiated EMI because it is an AC voltage at the switching frequency. It is always good practice to use a ground plane in the design, particularly at high currents.

The two ground pins, PWR GND and GND, should be connected by as short a trace as possible; they can be connected underneath the device. These pins are resistively connected internally by approximately 50 Ω. The ground pins should be tied to the ground plane, or to a large ground trace in close proximity to both the FB divider and C_OUT grounds.

The gate pin of the external PFET should be located close to the PGATE pin. However, if a very small FET is used, a resistor may be required between PGATE and the gate of the FET to reduce high frequency ringing. Because this resistor will slow the rise time of the PFET, the current limit blanking time should be taken into consideration (see Current Limit Operation).

The feedback voltage signal line can be sensitive to noise. Avoid inductive coupling to the inductor or the switching node, by keeping the FB trace away from these areas.

Layout Example

Figure 30. Top Layer,
Typical PCB Layout (3.3-V Output)

Figure 32. Silk Screen,
Typical PCB Layout (3.3-V Output)

Figure 31. Bottom Layer,
Typical PCB Layout (3.3-V Output)

Figure 33. Typical PCB Layout Schematic (3.3-V Output)