ZHCSLE0B August   2021  – August 2023 JFE2140

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 AC Measurement Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precision Matching
      2. 8.3.2 Ultra-Low Noise
      3. 8.3.3 Low Gate Current
      4. 8.3.4 Input Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Protection Diodes
      2. 9.1.2 Cascode Configuration
      3. 9.1.3 Common-Source Amplifier
      4. 9.1.4 Composite Amplifiers
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Noise, Low-Power, High-Input-Impedance Composite Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Front-End Design
        1. 9.2.2.1 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ 仿真软件（免费下载）
        3. 10.1.1.3 TI 参考设计
        4. 10.1.1.4 滤波器设计工具
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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9.2.1.2 Detailed Design Procedure

This design provides single-ended, adjustable gain from 15 dB to 40 dB with extremely high input impedance at a very low frequency response. The power consumption is optimized for battery-powered audio applications.

  • The JFE2140 is configured as a differential pair in a voltage-feedback composite amplifier. This configuration allows for low-frequency gain without large dc-blocking capacitors.
  • The bias current is set by selecting the desired bias current and noise tradeoff (see Figure 6-16). To set the bias current point, adjust the source resistance according to Figure 9-4.
  • After the bias current is selected, set the JFET stage gain as high as possible. To avoid pushing the device into the linear region of operation, use the largest drain resistor (RD1,2) possible while maintaining a minimum of 1 V across the drain-to-source nodes.
  • The overall gain can be configured with the feedback resistors RF1, RF2 and RF3. Capacitor CF3 can be required depending on the gain configuration for amplifier stability; use amplifier stability best practices to maintain stability at both maximum and minimum gain configurations.