ZHCSE09B June   2015  – March 2024 HD3SS3411-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable and Power Savings
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 AC Coupling Capacitors
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Critical Routes
        2. 7.4.1.2 General Routing/Placement Rules
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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7.1 Application Information

HD3SS3411-Q1 mux channels have independent adaptive common mode tracking allowing RX and TX paths to have different common-mode voltage simplifying system implementation and avoiding inter-operational issues.

HD3SS3411-Q1 mux does not provide common mode biasing for the channel. Therefore, it is required that the device is biased from either side for all active channels.

The HD3SS3411 supports several high-speed data protocols with a differential amplitude of < 1800 mVpp and a common-mode voltage of < 2V, as with USB 3.1 and DisplayPort 1.3. The one select input (SEL) pin can be controlled by an available GPIO pin within a system or from a microcontroller.