ZHCSE09B June   2015  – March 2024 HD3SS3411-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable and Power Savings
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 AC Coupling Capacitors
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Critical Routes
        2. 7.4.1.2 General Routing/Placement Rules
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

General Routing/Placement Rules

  • Follow 20H rule (H is the distance to ref-plane) for separation of the high speed trace from the edge of the plane.
  • Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines.
  • Route all differential pairs on the top or bottom layer (microstrip traces) if possible or on the same group of layers. Only use vias in the breakout region of the device if vias are necessary for routing. Avoid using vias in the main region of the board at all cost. Use a ground reference via next to signal via. Distance between ground reference via and signal need to be calculated to have similar impedance as traces.
  • Make sure not all differential signals are routed over a plane split. Changing signal layers is preferable to crossing plane splits.
  • Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for high frequency return current path.
  • Route differential traces over a continuous plane with no interruptions.
  • Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or any magnetic source.
  • Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keep out distance where possible.
  • Place the decoupling caps next to each power terminal on the HD3SS3411-Q1. Take care to minimize the stub length of the trace connecting the capacitor to the power pin.
  • Avoid sharing vias between multiple decoupling caps.
  • Place vias as close as possible to the decoupling cap solder pad.
  • Widen VCC/GND planes to reduce effect of static and dynamic IR drop.