ZHCSE09B June   2015  – March 2024 HD3SS3411-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable and Power Savings
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 AC Coupling Capacitors
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Critical Routes
        2. 7.4.1.2 General Routing/Placement Rules
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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6.1 Overview

The HD3SS3411-Q1 is a high-speed bi-directional passive switch in mux or demux configurations. Based on control pin SEL, the device switches one differential channels between Port B or Port C to Port A.

The HD3SS3411-Q1 is a generic analog differential passive switch that can work for any high speed interface applications as long as it is biased at a common-mode voltage range of 0V to 2V and has differential signaling with differential amplitude up to 1800 mVpp. The device offers adaptive tracking that allows users to keep the channel unchanged for the entire common-mode voltage range.

Table 6-1 MUX Pin Connections(1)
PORT A CHANNELPORT B OR PORT C CHANNEL CONNECTED TO PORT A CHANNEL
SEL = LSEL = H
ApBpCp
AnBnCn
(1) The HD3SS3411-Q1 can tolerate polarity inversions for all differential signals on Ports A, B and C. Take care to ensure the same polarity is maintained on Port A vs. Port B/C.