Table 5-1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK

Table 5-2 Current Consumption at 125-MHz C28x SYSCLKOUT and 125-MHz M3SSCLK

5.9.1 Power Sequencing

There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO199, are glitch-free during power up and power down.) No voltage larger than a diode drop (0.7 V) above V_DDIO should be applied to any digital pin before powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.

A. Upon power up, PLLSYSCLK is OSCCLK/8. Because the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT = OSCCLK/32 during this phase.

B. Boot ROM configures the SYSDIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that XCLKOUT will not be visible at the pin until explicitly configured by user code.

C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or without PLL enabled.

D. The XRS pin will be driven low by on-chip POR circuitry until the V_DDIO voltage crosses the POR threshold. (The POR threshold is lower than the operating voltage requirement.) To allow the external clock to stabilize, the XRS pin may also need to be driven low by the system for additional time.

Figure 5-1 Power-On Reset

A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or without PLL enabled.

Figure 5-2 Warm Reset

5.9.2 Clock Specifications

This section provides the frequencies and timing requirements of the input clocks; PLL lock times; frequencies of the internal clocks; and the frequency and switching characteristics of the output clock.

5.9.3 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

5.9.3.2 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.

A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.

Figure 5-3 3.3-V Test Load Circuit

5.9.4 Flash Timing – Master Subsystem

The equation to compute the Flash wait state in Table 5-20 is as follows:

round up to the next integer, or 1, whichever is larger.

5.9.5 Flash Timing – Control Subsystem

The equation to compute the Flash wait state in Table 5-25 is as follows:

round up to the next integer, or 1, whichever is larger.

5.9.6 GPIO Electrical Data and Timing

5.9.6.1 GPIO - Output Timing

Table 5-26 General-Purpose Output Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER			MIN	MAX	UNIT
tr(GPO)	Rise time, GPIO switching low to high	All GPIOs		8	ns
tf(GPO)	Fall time, GPIO switching high to low	All GPIOs		8	ns
tfGPO	Toggling frequency, GPIO pins			25	MHz

Figure 5-4 General-Purpose Output Timing

5.9.6.2 GPIO - Input Timing

Table 5-27 General-Purpose Input Timing Requirements

			MIN	MAX	UNIT
tw(SP)	Sampling period	QUALPRD = 0	1tc(SCO)		cycles
		QUALPRD ≠ 0	2tc(SCO) * QUALPRD		cycles
tw(IQSW)	Input qualifier sampling window		tw(SP) * (n(1) – 1)		cycles
tw(GPI) (2)	Pulse duration, GPIO low/high	Synchronous mode	2tc(SCO)		cycles
		With input qualifier	tw(IQSW) + tw(SP) + 1tc(SCO)		cycles

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.

(2) For t_w(GPI), pulse width is measured from V_IL to V_IL for an active low signal and V_IH to V_IH for an active high signal.

A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).

B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.

C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.

D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.

Figure 5-5 Sampling Mode

5.9.6.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier configurations.

Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.

Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0

Sampling frequency = SYSCLKOUT, if QUALPRD = 0

Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0

In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.

Sampling period = SYSCLKOUT cycle, if QUALPRD = 0

In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register.

Case 1:

Qualification using 3 samples

Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0

Case 2:

Qualification using 6 samples

Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0

Figure 5-6 General-Purpose Input Timing

5.9.6.4 Low-Power Mode Wakeup Timing

Table 5-28 shows the timing requirements, Table 5-29 shows the switching characteristics, and Figure 5-7 shows the timing diagram for IDLE mode.

Table 5-28 IDLE Mode Timing Requirements⁽¹⁾

			MIN	MAX	UNIT
tw(WAKE-INT)	Pulse duration, external wake-up signal	Without input qualifier	2tc(SCO)		cycles
		With input qualifier	5tc(SCO) + tw(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 5-27.

Table 5-29 IDLE Mode Switching Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
td(WAKE-IDLE)	Delay time, external wake signal to program execution resume (2)
	Wake-up from Flash Flash module in active state	Without input qualifier		20tc(SCO)	cycles
		With input qualifier		20tc(SCO) + tw(IQSW)
	Wake-up from Flash Flash module in sleep state	Without input qualifier		1050tc(SCO)	cycles
		With input qualifier		1050tc(SCO) + tw(IQSW)
	Wake-up from SARAM	Without input qualifier		20tc(SCO)	cycles
		With input qualifier		20tc(SCO) + tw(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 5-27.

(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up) signal involves additional latency.

A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.

B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed.

Figure 5-7 IDLE Entry and Exit Timing

Table 5-30 STANDBY Mode Timing Requirements

				MIN	MAX	UNIT
tw(WAKE-INT)	Pulse duration, external wake-up signal		Without input qualification	3tc(OSCCLK)		cycles
			With input qualification(1)	(2 + QUALSTDBY) * tc(OSCCLK)

(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.

Table 5-31 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
td(IDLE-XCOL)	Delay time, IDLE instruction executed to XCLKOUT low		32tc(SCO)	45tc(SCO)	cycles
td(WAKE-STBY)	Delay time, external wake signal to program execution resume(1)				cycles
	Wake up from flash Flash module in active state	Without input qualifier		100tc(SCO)	cycles
		With input qualifier		100tc(SCO) + tw(WAKE-INT)
	Wake up from flash Flash module in sleep state	Without input qualifier		1125tc(SCO)	cycles
		With input qualifier		1125tc(SCO) + tw(WAKE-INT)
	Wake up from SARAM	Without input qualifier		100tc(SCO)	cycles
		With input qualifier		100tc(SCO) + tw(WAKE-INT)

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up signal) involves additional latency.

A. IDLE instruction is executed to put the device into STANDBY mode.

B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off:

• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this number then it will fail.  It is recommended to enter STANDBY mode from SARAM without an XINTF access in progress.

C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.

D. The external wake-up signal is driven active.

E. After a latency period, the STANDBY mode is exited.

F. Normal execution resumes. The device will respond to the interrupt (if enabled).

G. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed.

Figure 5-8 STANDBY Entry and Exit Timing Diagram

Table 5-32 HALT Mode Timing Requirements

			MIN	MAX	UNIT
tw(WAKE-GPIO)	Pulse duration, GPIO wake-up signal		toscst + 2tc(OSCCLK)(1)		cycles
tw(WAKE-XRS)	Pulse duration, XRS wakeup signal		toscst + 8tc(OSCCLK)		cycles

(1) See Table 5-4 for an explanation of t_oscst.

Table 5-33 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
td(IDLE-XCOL)	Delay time, IDLE instruction executed to XCLKOUT low	32tc(SCO)	45tc(SCO)	cycles
tp	PLL lock-up time		131072tc(OSCCLK)	cycles
td(WAKE-HALT)	Delay time, PLL lock to program execution resume Wake up from flash Flash module in sleep state		1125tc(SCO)	cycles
	Wake up from SARAM		35tc(SCO)	cycles

A. IDLE instruction is executed to put the device into HALT mode.

B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off and the CLKIN to the core is stopped:

• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this number then it will fail.  It is recommended to enter HALT mode from SARAM without an XINTF access in progress.

C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.

D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be taken to maintain a low noise environment before entering and during HALT mode.

E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or XCLKIN) cycles. Note that these 131,072 clock cycles are applicable even when the PLL is disabled (that is, code execution will be delayed by this duration even when the PLL is disabled).

F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after a latency.

G. Normal operation resumes.

H. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed.

Figure 5-9 HALT Wake-Up Using GPIOn

5.9.7 External Interrupt Electrical Data and Timing

Figure 5-10 External Interrupt Timing

5.10.1 Analog-to-Digital Converter

Figure 5-11 shows the internal structure of each of the two ADC peripherals that are present on Concerto. Each ADC has 16 channels that can be programmed to select analog inputs, select start-of-conversion trigger, set the sampling window, and select end-of-conversion interrupt to prompt a CPU or DMA to read 16 result registers. The 16 ADC channels can be used independently or in pairs, based on the assignments inside the SAMPLEMODE register. Pairing up the channels allows two analog inputs to be sampled simultaneously—thereby, increasing the overall conversion performance.

Figure 5-11 ADC

5.10.1.5 ADC Electrical Data and Timing

Table 5-36 ADC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
DC SPECIFICATIONS
Resolution			12		Bits
ADC clock		2		37.5	MHz
Sample Window		7		64	ADC clocks
ACCURACY
INL (Integral nonlinearity)		–4		4	LSB
DNL (Differential nonlinearity)		–1		1.5	LSB
Offset error	Executing a single self-recalibration	–20	0	20	LSB
	Executing periodic self-recalibration	–4	0	4
Overall gain error with internal reference		–60		60	LSB
Overall gain error with external reference		–40		40	LSB
Channel-to-channel offset variation		–4		4	LSB
Channel-to-channel gain variation		–4		4	LSB
VREFLO input current			–100		µA
VREFHI input current			100		µA
ANALOG INPUT
Analog input voltage with internal reference		0		3.3	V
Analog input voltage with external reference		VREFLO		VREFHI	V
VREFLO input voltage		VSSA		0.66	V
VREFHI input voltage		2.64		VDDA	V
Input capacitance			5		pF
Input leakage current			±2		μA
ADDITIONAL
ADC SNR			65		dB
ADC SINAD			62		dB
ADC THD (50 kHz)			–65		dB
ENOB (SNR)			10.1		Bits
SFDR			66		dB

A. Gain error contribution is based on sampling of full-scale voltage using internal reference mode.

B. Periodic ADC offset recalibration is assumed.

C. Total error shown represents the absolute value of possible error.

Figure 5-12 Typical ADC Total Error
[Temperature (°C) versus Total Error (LSBs)]

Table 5-37 External ADC Start-of-Conversion Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
tw(ADCSOCL)	Pulse duration, ADCSOCxO low	32tc(HCO)		cycles

Figure 5-13 ADCSOCAO or ADCSOCBO Timing

5.10.2 Comparator + DAC Units

Figure 5-14 shows the internal structure of the six analog Comparator + DAC units present in Concerto devices. Each unit compares two analog inputs (A and B) and assigns a value of ‘1’ when the voltage of the A input is greater than that of the B input, or a value of ‘0’ when the opposite is true. The six A inputs and six B inputs come from AIO_MUX1 and AIO_MUX2. All six B inputs can also be provided by the 10-bit digital-to-analog units that are present in each comparator DAC. The 10-bit value for each DAC unit is programmed in the respective DACVAL register. Another comparator register, COMPCTL, can be programmed to select the source of the B input, to enable or disable the comparator circuit, to invert comparator output, to synchronize comparator output to C28x SYSCLK, and to select the qualification period (number of clock cycles). All six output signals from the six comparators can be routed out to the device pins via GPIO_MUX2 pin mux.

Figure 5-14 Comparator + DAC Units

5.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing

Table 5-38 Electrical Characteristics of the Comparator/DAC

over recommended operating conditions (unless otherwise noted)

PARAMETER	MIN	TYP	MAX	UNITS
Comparator
Comparator Input Range		VSSA – VDDA		V
Comparator response time to PWM Trip Zone (Async)		30		ns
Input Offset		±5		mV
Input Hysteresis(1)		35		mV
DAC
DAC Output Range		VSSA – VDDA		V
DAC resolution		10		bits
DAC settling time		See Figure 5-15
DAC Gain		–1.5		%
DAC Offset		10		mV
Monotonic		Yes
INL		±3		LSB

(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback resistance between the output of the comparator and the noninverting input of the comparator.

Figure 5-15 DAC Settling Time

5.10.3 Interprocessor Communications

Figure 5-16 shows the internal structure of the IPC peripheral used to synchronize program execution and exchange of data between the Cortex-M3 and the C28x CPU. IPC can be used by itself when synchronizing program execution or it can be used in conjunction with Message RAMs when coordinating data transfers between processors. In either case, the operation of the IPC is the same. There are two independent sides to the IPC peripheral—MTOC (Master to Control) and CTOM (Control to Master).

The MTOC IPC is used by the Master Subsystem to send events to the Control Subsystem. The MTOC IPC typically sends events to the Control Subsystem by using the following registers: MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS ⁽¹⁾, and MTOCIPCACK. Each of the 32 bits of these registers represents 32 independent channels through which the Cortex-M3 CPU can send up to 32 events to the C28x CPU via software handshaking. Additionally, the first 4 bits of the MTOCIPC registers are supplemented with interrupts. To send an event via channel 2 from Cortex-M3 to C28x, for example, the Cortex-M3 and C28x CPUs use bit 2 of the MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS, MTOCIPCACK registers. The handshake starts with the Cortex-M3 polling bit 2 of the MTOCIPCFLG register to make sure bit 2 is ‘0’. Next, the Cortex-M3 writes a ‘1’ into bit 2 of the MTOCIPCSET register to start the handshake. In the mean time, the C28x is continually polling the MTOCIPCSTS register while waiting for the message. As soon as the Cortex-M3 writes ‘1’ to bit 2 of the MTOCIPCSET register, bit 2 of MTOCIPCFLG/MTOCIPCSTS also turns ‘1’, thus announcing the event to the C28x. As soon as the C28x CPU reads a ‘1’ from the MTOCIPCSTS register, the C28x CPU should acknowledge by writing a ‘1’ to bit 2 of the MTOCIPCACK register, which in turn, clears bit 2 of the MTOCIPCFLG/MTOCIPCSTS register, enabling the Cortex-M3 to send another message. Because the first four channels (bits 0, 1, 2, 3) are backed up by interrupts, both processors in the above example can use IPC interrupt 2 instead of polling to increase performance.

A similar handshake is also used when sending data (not just event) from the Master Subsystem to the Control Subsystem, but with two additional steps. Before setting a bit in the MTOCIPCSET register, the Cortex-M3 should first load the MTOC Message RAM with a block of data that is to be made available to the C28x. In the second additional step, the C28x should read the data before setting a bit in the MTOCIPCACK register. This way, no data gets lost during multiple data transfers through a given block of the message RAM.

The CTOM IPC is used by the Control Subsystem to send events to the Master Subsystem. The CTOM IPC typically sends events to the Master Subsystem by using the following three registers: CTOMIPCSET, CTOMIPCFLG/CTOMIPCSTS, and CTOMIPCACK. The process is exactly the same as that for the MTOC IPC communication above.

5.10.4 External Peripheral Interface

The EPI provides a high-speed parallel bus for interfacing external peripherals and memory. EPI is accessible from both the Master Subsystem and the Control Subsystem. EPI has several modes of operation to enable glueless connectivity to most types of external devices. Some EPI modes of operation conform to standard microprocessor address/data bus protocols, while others are tailored to support a variety of fast custom interfaces, such as those communicating with field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs).

The EPI peripheral can be accessed by the Cortex-M3 CPU, the Cortex-M3 DMA, the C28x CPU, and the C28x DMA over the high-performance AHB bus. The Cortex-M3 CPU and the µDMA drive AHB bus cycles directly through the Cortex-M3 Bus Matrix. The C28x CPU and DMA also connect to the Cortex-M3 Bus Matrix, but not directly. Before entering the Cortex-M3 Bus Matrix, the native C28x CPU and DMA bus cycles are first converted to AHB protocol inside the MEM32-to-AHB Bus Bridge. After that, they pass through the Frequency Gasket to reduce the bus frequency by a factor of 2 or 4. Inside the Cortex-M3 Bus Matrix, the Cortex-M3 bus cycles may have to compete with C28x bus cycles for access to the AHB bus on the way to the EPI peripheral. See Figure 5-17 to see how EPI interfaces to the Concerto Master Subsystem, the Concerto Control Subsystem, Resets, Clocks, and Interrupts.

Depending on how the Real-Time Window registers are configured inside the Bus Matrix, the arbitration between the Cortex-M3 and C28x bus cycles is fixed-priority with Cortex-M3 having higher priority than C28x, or the C28x having the option to own the Bus Matrix for a fixed period of time (window)—effectively stalling all Cortex-M3 accesses during that time. Another EPI register inside the Cortex-M3 Bus Matrix is the Memory Protection Register, which enables assignments of chip-select spaces to Cortex-M3 or C28x EPI accesses (or both). The assignments of chip-select spaces prevent a bus cycle (from any processor) that does not own a given chip-select space, from getting through to EPI. The Real-time Window registers are the only EPI-related registers that are configurable by the C28x. The Memory Protection Register is configurable only by the Cortex-M3 CPU, as are all configuration registers inside the EPI peripheral. Figure 5-17 shows the EPI registers and how they relate to individual blocks within the EPI.

Once a bus cycle arrives at the AHB bus interface inside the EPI peripheral, the bus cycle is routed to the General-Purpose Block, SDRAM Block, or the Host Bus Module, depending on the operating mode chosen through the EPI Configuration Register. Write cycles are buffered in a 4-word-deep Write FIFO; therefore, in most cases, the write cycles do not stall the CPU or DMA unless the Write FIFO becomes full. Read cycles can be handled in two different ways: blocking read cycles and nonblocking read cycles. Blocking read cycles are implemented when the content of a Read Data Register is 0. Blocking reads stall the CPU or DMA until the bus transaction completes. Nonblocking read cycles are triggered when a non-zero value is written into a Read Data Register. A non-zero value being written into a Read Data register triggers EPI to autonomously perform multiple data reads in the background (without involving CPU or DMA) according to values stored inside the Read Address Register and the Read Size Register. The incoming data is then temporarily stored in the Non-Blocking Read (NBR) FIFO until an EPI interrupt is generated to prompt the CPU or DMA to read the FIFO without risk of stalling. Furthermore, EPI has actually two sets of Data/Address/Size registers (set 0 and set 1) to enable ping-pong operation of nonblocking reads. In a ping-pong operation, while the previously fetched data is being read by the CPU or DMA from one end of the NBR FIFO, the next set of data words is simultaneously being deposited into the other end of the NBR FIFO.

Figure 5-17 EPI

EPI can directly interrupt the Cortex-M3 CPU, the Cortex-M3 uDMA, and the C28x CPU (but not the C28x DMA) via the EPI interrupt. Typically, EPI interrupts are used to prompt the CPU or DMA to move data to and from EPI. There are four EPI Interrupt registers that control various facets of interrupt generation, clearing, and masking. The EPI Interrupt can trigger µDMA to perform reads and writes through DMA Channels 20 and 22. If a CPU is the intended recipient, the Cortex-M3 CPU is interrupted by NVIC vector 69, and the C28x CPU is interrupted through the INT12/INTx6 vector to the PIE.

During EPI bus cycles, addresses entering the EPI module can propagate unchanged to the pins, or be remapped to different addresses according to values stored in the EPI Address Map Register in conjunction with the most significant bit of the incoming address.

The EPI's three primary operating modes are: the General-Purpose Mode, the SDRAM Mode, and the Host Bus Mode (including 8-bit and 16-bit versions).

5.10.4.1 EPI General-Purpose Mode

The EPI General-Purpose Mode is designed for high-speed clocked interfaces such as ones communicating with FPGAs and CPLDs. The high-speed clocked interfaces are different from the slower Host Bus interfaces, which have more relaxed timings that are compatible with established protocols like ones used to communicate with 8051 devices. Support of bus cycle framing and precisely controlled clocking are the additional features of the General-Purpose Mode that differentiate the General-Purpose Mode from the 8-bit and 16-bit Host Bus Modes.

Framing allows multiple bus transactions to be grouped together with an output signal called FRAME. The slave device responding to the bus cycles may use this signal to recognize related words of data and to speed up their transfers. The frame lengths are programmable and may vary from 1 to 30 clocks, depending on the clocking mode used.

Precise clocking is accomplished with a dedicated clock output pin (CLK). Devices responding the bus cycles can synchronize to CLK for faster transfers. The clock frequency can be precisely controlled through the Baud Rate Control block. This output clock can be gated or free-running. A gated approach uses a setup-time model in which the EPI clock controls when bus transactions are starting and stopping. A free-running EPI clock requires another method for determining when data is live, such as the frame pin or RD/WR strobes.

These and numerous other aspects of the General-Purpose Mode are controlled through the General-Purpose Configuration Register and the General-Purpose Configuration2 Register. The clocking for the General-Purpose Mode is configured through the EPI Baud Register of the EPI Baud Rate Control block.

See Figure 5-18 for a snapshot of the General-Purpose Mode registers, modes, and features. For more detailed maps of the General-Purpose Mode, see Table 5-39.

Figure 5-18 EPI General-Purpose Modes

Table 5-39 EPI MODES – General-Purpose Mode (EPICFG/MODE = 0x0)

EPI PORT NAME		EPI SIGNAL FUNCTION				DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	GENERAL-PURPOSE SIGNAL (D8, A20)	GENERAL-PURPOSE SIGNAL (D16, A12)	GENERAL-PURPOSE SIGNAL (D24, A4)	GENERAL-PURPOSE SIGNAL (D30, NO ADDR)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		D0	D0	D0	D0	PH3_GPIO51
EPI0S1		D1	D1	D1	D1	PH2_GPIO50
EPI0S2		D2	D2	D2	D2	PC4_GPIO68
EPI0S3		D3	D3	D3	D3	PC5_GPIO69
EPI0S4		D4	D4	D4	D4	PC6_GPIO70
EPI0S5		D5	D5	D5	D5	PC7_GPIO71
EPI0S6		D6	D6	D6	D6	PH0_GPIO48
EPI0S7		D7	D7	D7	D7	PH1_GPIO49
EPI0S8		A0	D8	D8	D8	PE0_GPIO24
EPI0S9		A1	D9	D9	D9	PE1_GPIO25
EPI0S10		A2	D10	D10	D10	PH4_GPIO52
EPI0S11		A3	D11	D11	D11	PH5_GPIO53
EPI0S12		A4	D12	D12	D12	PF4_GPIO36
EPI0S13		A5	D13	D13	D13	PG0_GPIO40
EPI0S14		A6	D14	D14	D14	PG1_GPIO41
EPI0S15		A7	D15	D15	D15	PF5_GPIO37
EPI0S16		A8	A0	D16	D16	PJ0_GPIO56
EPI0S17		A9	A1	D17	D17	PJ1_GPIO57
EPI0S18		A10	A2	D18	D18	PJ2_GPIO58
EPI0S19		A11	A3	D19	D19	PD4_GPIO20	PJ3_GPIO59
EPI0S20		A12	A4	D29	D29	PD2_GPIO18
EPI0S21		A13	A5	D21	D21	PD3_GPIO19
EPI0S22		A14	A6	D22	D22	PB5_GPIO13
EPI0S23		A15	A7	D23	D23	PB4_GPIO12
EPI0S24		A16	A8	A0	D24	PE2_GPIO26
EPI0S25		A17	A9	A1	D25	PE3_GPIO27
EPI0S26		A18	A10	A2	D26	PH6_GPIO54
EPI0S27		A19/RDY	A11/RDY	A3/RDY	D27	PH7_GPIO55
EPI0S28		WR	WR	WR	D28	PD5_GPIO21	PJ4_GPIO60
EPI0S29		RD	RD	RD	D29	PD6_GPIO22	PJ5_GPIO61
EPI0S30		FRAME	FRAME	FRAME	D30	PD7_GPIO23	PJ6_GPIO62
EPI0S31		CLK	CLK	CLK	D31	PG7_GPIO47
EPI0S32		x	x	x	x	PF2_GPIO34	PC0_GPIO64
EPI0S33		x	x	x	x	PF3_GPIO35	PC1_GPIO65
EPI0S34		x	x	x	x	PE4_GPIO28
EPI0S35		x	x	x	x	PE5_GPIO29
EPI0S36		x	x	x	x	PB7_GPIO15	PC3_GPIO67
EPI0S37		x	x	x	x	PB6_GPIO14	PC2_GPIO66
EPI0S38		x	x	x	x	PF6_GPIO38	PE4_GPIO28
EPI0S39		x	x	x	x	PG2_GPIO42
EPI0S40		x	x	x	x	PG5_GPIO45
EPI0S41		x	x	x	x	PG6_GPIO46
EPI0S42		x	x	x	x	PN6_GPIO102
EPI0S43		x	x	x	x	PN7_GPIO103

5.10.4.2 EPI SDRAM Mode

The EPI SDRAM Mode combines high performance, low cost, and low pin use to access up to 512 megabits (Mb) of external memory. Main features of the EPI SDRAM interface are:

• Supports x16 (single data rate) SDRAM
• Supports low-cost SDRAMs up to 64 megabytes (MB) [or 512Mb]
• Includes automatic refresh and access to all banks, rows
• Includes Sleep/STANDBY Mode to keep contents active with minimal power drain
• Multiplexed address/data interface for reduced pin count

See Figure 5-19 for a snapshot of the SDRAM Mode registers and supported memory sizes. For more detailed maps of the SDRAM Mode, see Table 5-40.

Figure 5-19 EPI SDRAM Mode

Table 5-40 EPI MODES – SDRAM Mode (EPICFG/MODE = 0x1)

EPI PORT NAME		EPI SIGNAL FUNCTION		DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	COLUMN/ROW ADDRESS	DATA	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		A0	D0	PH3_GPIO51
EPI0S1		A1	D1	PH2_GPIO50
EPI0S2		A2	D2	PC4_GPIO68
EPI0S3		A3	D3	PC5_GPIO69
EPI0S4		A4	D4	PC6_GPIO70
EPI0S5		A5	D5	PC7_GPIO71
EPI0S6		A6	D6	PH0_GPIO48
EPI0S7		A7	D7	PH1_GPIO49
EPI0S8		A8	D8	PE0_GPIO24
EPI0S9		A9	D9	PE1_GPIO25
EPI0S10		A10	D10	PH4_GPIO52
EPI0S11		A11	D11	PH5_GPIO53
EPI0S12		A12	D12	PF4_GPIO36
EPI0S13		BA0	D13	PG0_GPIO40
EPI0S14		BA1	D14	PG1_GPIO41
EPI0S15		D15		PF5_GPIO37
EPI0S16		DQML		PJ0_GPIO56
EPI0S17		DQMH		PJ1_GPIO57
EPI0S18		CAS		PJ2_GPIO58
EPI0S19		RAS		PD4_GPIO20	PJ3_GPIO59
EPI0S28		WE		PD5_GPIO21	PJ4_GPIO60
EPI0S29		CS		PD6_GPIO22	PJ5_GPIO61
EPI0S30		CKE		PD7_GPIO23	PJ6_GPIO62
EPI0S31		CLK		PG7_GPIO47
EPI0S20		x		PD2_GPIO18
EPI0S21		x		PD3_GPIO19
EPI0S22		x		PB5_GPIO13
EPI0S23		x		PB4_GPIO12
EPI0S24		x		PE2_GPIO26
EPI0S25		x		PE3_GPIO27
EPI0S26		x		PH6_GPIO54
EPI0S27		x		PH7_GPIO55
EPI0S32		x		PF2_GPIO34	PC0_GPIO64
EPI0S33		x		PF3_GPIO35	PC1_GPIO65
EPI0S34		x		PE4_GPIO28
EPI0S35		x		PE5_GPIO29
EPI0S36		x		PB7_GPIO15	PC3_GPIO67
EPI0S37		x		PB6_GPIO14	PC2_GPIO66
EPI0S38		x		PF6_GPIO38	PE4_GPIO28
EPI0S39		x		PG2_GPIO42
EPI0S40		x		PG5_GPIO45
EPI0S41		x		PG6_GPIO46
EPI0S42		x		PN6_GPIO102
EPI0S43		x		PN7_GPIO103

5.10.4.3 EPI Host Bus Mode

There are two versions of the EPI Host Bus Mode: an 8-bit version (HB-8) and a 16-bit version (HB-16). Section 5.10.4.3.1 discusses the EPI 8-Bit Host Bus Mode. Section 5.10.4.3.2 discusses the EPI 16-Bit Host Bus Mode.

5.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode

The 8-Bit Host Bus (HB-8) Mode uses fewer data pins than the 16-Bit Host Bus (HB-16) Mode; hence, more pins are available for address. The HB-8 Mode is also slower than the General-Purpose Mode in order to accommodate older logic. The HB-8 Mode is selected with the MODE field of EPI Configuration Register. Within the HB-8 Mode, two additional registers are used to select address/data muxing, chip selects, and other options. These registers are the HB-8 Configuration Register and the HB-8 Configuration2 Register. See Figure 5-20 for a snapshot of HB-8 registers, modes, and features.

Figure 5-20 EPI 8-Bit Host Bus Mode

5.10.4.3.1.1 HB-8 Muxed Address/Data Mode

The HB-8 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-8 Muxed Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the HB-8 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; and 1–4 CS (chip select) signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Muxed Mode, see Table 5-41.

Table 5-41 EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Muxed (EPIHB16CFG/MODE = 0x0)

EPI PORT NAME		EPI SIGNAL FUNCTION				DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH ADDRESS LATCH ENABLE (CSCFG = 0x0)	WITH ONE CHIP SELECT (CSCFG = 0x1)	WITH TWO CHIP SELECTS (CSCFG = 0x2)	WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		AD0	AD0	AD0	AD0	PH3_GPIO51
EPI0S1		AD1	AD1	AD1	AD1	PH2_GPIO50
EPI0S2		AD2	AD2	AD2	AD2	PC4_GPIO68
EPI0S3		AD3	AD3	AD3	AD3	PC5_GPIO69
EPI0S4		AD4	AD4	AD4	AD4	PC6_GPIO70
EPI0S5		AD5	AD5	AD5	AD5	PC7_GPIO71
EPI0S6		AD6	AD6	AD6	AD6	PH0_GPIO48
EPI0S7		AD7	AD7	AD7	AD7	PH1_GPIO49
EPI0S8		A8	A8	A8	A8	PE0_GPIO24
EPI0S9		A9	A9	A9	A9	PE1_GPIO25
EPI0S10		A10	A10	A10	A10	PH4_GPIO52
EPI0S11		A11	A11	A11	A11	PH5_GPIO53
EPI0S12		A12	A12	A12	A12	PF4_GPIO36
EPI0S13		A13	A13	A13	A13	PG0_GPIO40
EPI0S14		A14	A14	A14	A14	PG1_GPIO41
EPI0S15		A15	A15	A15	A15	PF5_GPIO37
EPI0S16		A16	A16	A16	A16	PJ0_GPIO56
EPI0S17		A17	A17	A17	A17	PJ1_GPIO57
EPI0S18		A18	A18	A18	A18	PJ2_GPIO58
EPI0S19		A19	A19	A19	A19	PD4_GPIO20	PJ3_GPIO59
EPI0S20		A20	A20	A20	A20	PD2_GPIO18
EPI0S21		A21	A21	A21	A21	PD3_GPIO19
EPI0S22		A22	A22	A22	A22	PB5_GPIO13
EPI0S23		A23	A23	A23	A23	PB4_GPIO12
EPI0S24		A24	A24	A24	A24	PE2_GPIO26
EPI0S25		A25	A25	A25	A25	PE3_GPIO27
EPI0S26		A26	A26	A26	CS0	PH6_GPIO54
EPI0S27		A27	A27	CS1	CS1	PH7_GPIO55
EPI0S30		ALE	CS0	CS0	ALE	PD7_GPIO23	PJ6_GPIO62
EPI0S29		WR	WR	WR	WR	PD6_GPIO22	PJ5_GPIO61
EPI0S28		RD	RD	RD	RD	PD5_GPIO21	PJ4_GPIO60
EPI0S31		x	x	x	x	PG7_GPIO47
EPI0S32		x	x	x	x	PF2_GPIO34	PC0_GPIO64
EPI0S33		x	x	x	x	PF3_GPIO35	PC1_GPIO65
EPI0S34		x	x	x	x	PE4_GPIO28
EPI0S35		x	x	x	x	PE5_GPIO29
EPI0S36		x	x	x	x	PB7_GPIO15	PC3_GPIO67
EPI0S37		x	x	x	x	PB6_GPIO14	PC2_GPIO66
EPI0S38		x	x	x	x	PF6_GPIO38	PE4_GPIO28
EPI0S39		x	x	x	x	PG2_GPIO42
EPI0S40		x	x	x	x	PG5_GPIO45
EPI0S41		x	x	x	x	PG6_GPIO46
EPI0S42		x	x	x	x	PN6_GPIO102
EPI0S43		x	x	x	x	PN7_GPIO103

5.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode

The HB-8 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-8 Non-Muxed Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the HB-8 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; and 1–4 CS (chip select) signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Non-Muxed Mode, see Table 5-42.

Table 5-42 EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Non-Muxed (EPIHB16CFG/MODE = 0x1)

EPI PORT NAME		EPI SIGNAL FUNCTION				DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH ADDRESS LATCH ENABLE (CSCFG = 0x0)	WITH ONE CHIP SELECT (CSCFG = 0x1)	WITH TWO CHIP SELECTS (CSCFG = 0x2)	WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		D0	D0	D0	D0	PH3_GPIO51
EPI0S1		D1	D1	D1	D1	PH2_GPIO50
EPI0S2		D2	D2	D2	D2	PC4_GPIO68
EPI0S3		D3	D3	D3	D3	PC5_GPIO69
EPI0S4		D4	D4	D4	D4	PC6_GPIO70
EPI0S5		D5	D5	D5	D5	PC7_GPIO71
EPI0S6		D6	D6	D6	D6	PH0_GPIO48
EPI0S7		D7	D7	D7	D7	PH1_GPIO49
EPI0S8		A0	A0	A0	A0	PE0_GPIO24
EPI0S9		A1	A1	A1	A1	PE1_GPIO25
EPI0S10		A2	A2	A2	A2	PH4_GPIO52
EPI0S11		A3	A3	A3	A3	PH5_GPIO53
EPI0S12		A4	A4	A4	A4	PF4_GPIO36
EPI0S13		A5	A5	A5	A5	PG0_GPIO40
EPI0S14		A6	A6	A6	A6	PG1_GPIO41
EPI0S15		A7	A7	A7	A7	PF5_GPIO37
EPI0S16		A8	A8	A8	A8	PJ0_GPIO56
EPI0S17		A9	A9	A9	A9	PJ1_GPIO57
EPI0S18		A10	A10	A10	A10	PJ2_GPIO58
EPI0S19		A11	A11	A11	A11	PD4_GPIO20	PJ3_GPIO59
EPI0S20		A12	A12	A12	A12	PD2_GPIO18
EPI0S21		A13	A13	A13	A13	PD3_GPIO19
EPI0S22		A14	A14	A14	A14	PB5_GPIO13
EPI0S23		A15	A15	A15	A15	PB4_GPIO12
EPI0S24		A16	A16	A16	A16	PE2_GPIO26
EPI0S25		A17	A17	A17	A17	PE3_GPIO27
EPI0S26		A18	A18	A18	CS0	PH6_GPIO54
EPI0S27		A19	A19	CS1	CS1	PH7_GPIO55
EPI0S30		ALE	CS0	CS0	ALE	PD7_GPIO23	PJ6_GPIO62
EPI0S29		WR	WR	WR	WR	PD6_GPIO22	PJ5_GPIO61
EPI0S28		RD	RD	RD	RD	PD5_GPIO21	PJ4_GPIO60
EPI0S31		x	x	x	x	PG7_GPIO47
EPI0S32		x	x	x	x	PF2_GPIO34	PC0_GPIO64
EPI0S33		x	x	x	x	PF3_GPIO35	PC1_GPIO65
EPI0S34		x	x	x	x	PE4_GPIO28
EPI0S35		x	x	x	x	PE5_GPIO29
EPI0S36		x	x	x	x	PB7_GPIO15	PC3_GPIO67
EPI0S37		x	x	x	x	PB6_GPIO14	PC2_GPIO66
EPI0S38		x	x	x	x	PF6_GPIO38	PE4_GPIO28
EPI0S39		x	x	x	x	PG2_GPIO42
EPI0S40		x	x	x	x	PG5_GPIO45
EPI0S41		x	x	x	x	PG6_GPIO46
EPI0S42		x	x	x	x	PN6_GPIO102
EPI0S43		x	x	x	x	PN7_GPIO103

5.10.4.3.1.3 HB-8 FIFO Mode

The HB-8 FIFO Mode uses 8 bits of data, removes ALE and address pins, and optionally adds external FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configuration (FIFO through block RAM). This FIFO Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA accesses. For more detailed maps of the HB-8 FIFO Mode, see Table 5-43.

Table 5-43 EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
FIFO Mode (EPIHB16CFG/MODE = 0x3)

EPI PORT NAME		EPI SIGNAL FUNCTION		DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH ONE CHIP SELECT (CSCFG = 0x1)	WITH TWO CHIP SELECTS (CSCFG = 0x2)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		D0	D0	PH3_GPIO51
EPI0S1		D1	D1	PH2_GPIO50
EPI0S2		D2	D2	PC4_GPIO68
EPI0S3		D3	D3	PC5_GPIO69
EPI0S4		D4	D4	PC6_GPIO70
EPI0S5		D5	D5	PC7_GPIO71
EPI0S6		D6	D6	PH0_GPIO48
EPI0S7		D7	D7	PH1_GPIO49
EPI0S25		x	CS1	PE3_GPIO27
EPI0S30		CS0	CS0	PD7_GPIO23	PJ6_GPIO62
EPI0S27		FFULL	FFULL	PH7_GPIO55
EPI0S26		FEMPTY	FEMPTY	PH6_GPIO54
EPI0S29		WR	WR	PD6_GPIO22	PJ5_GPIO61
EPI0S28		RD	RD	PD5_GPIO21	PJ4_GPIO60
EPI0S8		x	x	PE0_GPIO24
EPI0S9		x	x	PE1_GPIO25
EPI0S10		x	x	PH4_GPIO52
EPI0S11		x	x	PH5_GPIO53
EPI0S12		x	x	PF4_GPIO36
EPI0S13		x	x	PG0_GPIO40
EPI0S14		x	x	PG1_GPIO41
EPI0S15		x	x	PF5_GPIO37
EPI0S16		x	x	PJ0_GPIO56
EPI0S17		x	x	PJ1_GPIO57
EPI0S18		x	x	PJ2_GPIO58
EPI0S19		x	x	PD4_GPIO20	PJ3_GPIO59
EPI0S20		x	x	PD2_GPIO18
EPI0S21		x	x	PD3_GPIO19
EPI0S22		x	x	PB5_GPIO13
EPI0S23		x	x	PB4_GPIO12
EPI0S24		x	x	PE2_GPIO26
EPI0S32		x	x	PF2_GPIO34	PC0_GPIO64
EPI0S31		x	x	PG7_GPIO47
EPI0S33		x	x	PF3_GPIO35	PC1_GPIO65
EPI0S34		x	x	PE4_GPIO28
EPI0S35		x	x	PE5_GPIO29
EPI0S36		x	x	PB7_GPIO15	PC3_GPIO67
EPI0S37		x	x	PB6_GPIO14	PC2_GPIO66
EPI0S38		x	x	PF6_GPIO38	PE4_GPIO28
EPI0S39		x	x	PG2_GPIO42
EPI0S40		x	x	PG5_GPIO45
EPI0S41		x	x	PG6_GPIO46
EPI0S42		x	x	PN6_GPIO102
EPI0S43		x	x	PN7_GPIO103

5.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode

The 16-Bit Host Bus (HB-16) Mode uses fewer address pins than the 8-Bit Host Bus (HB-8) Mode; hence, more pins are available for data. The HB-16 Mode is also slower than the General-Purpose Mode in order to accommodate older logic. The HB-16 Mode is selected with the MODE field of EPI Configuration Register. Within the HB-16 Mode, two additional registers are used to select address/data muxing, byte selects, chip selects, and other options. These registers are the HB-16 Configuration Register and the
HB-16 Configuration2 Register. See Figure 5-21 for a snapshot of HB-16 registers, modes, and features.

Figure 5-21 EPI 16-Bit Host Bus Mode

5.10.4.3.2.1 HB-16 Muxed Address/Data Mode

The HB-16 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-16 Muxed Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (chip select) signals to enable one of four external peripherals; and two BSEL (byte select) signals to accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For more detailed maps of the HB-16 Muxed Mode without Byte Selects, see Table 5-44. For more detailed maps of the HB-16 Muxed Mode with Byte Selects, see Table 5-45.

Table 5-44 EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)

EPI PORT NAME		EPI SIGNAL FUNCTION				DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH ADDRESS LATCH ENABLE (CSCFG = 0x0)	WITH ONE CHIP SELECT (CSCFG = 0x1)	WITH TWO CHIP SELECTS (CSCFG = 0x2)	WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		AD0	AD0	AD0	AD0	PH3_GPIO51
EPI0S1		AD1	AD1	AD1	AD1	PH2_GPIO50
EPI0S2		AD2	AD2	AD2	AD2	PC4_GPIO68
EPI0S3		AD3	AD3	AD3	AD3	PC5_GPIO69
EPI0S4		AD4	AD4	AD4	AD4	PC6_GPIO70
EPI0S5		AD5	AD5	AD5	AD5	PC7_GPIO71
EPI0S6		AD6	AD6	AD6	AD6	PH0_GPIO48
EPI0S7		AD7	AD7	AD7	AD7	PH1_GPIO49
EPI0S8		AD8	AD8	AD8	AD8	PE0_GPIO24
EPI0S9		AD9	AD9	AD9	AD9	PE1_GPIO25
EPI0S10		AD10	AD10	AD10	AD10	PH4_GPIO52
EPI0S11		AD11	AD11	AD11	AD11	PH5_GPIO53
EPI0S12		AD12	AD12	AD12	AD12	PF4_GPIO36
EPI0S13		AD13	AD13	AD13	AD13	PG0_GPIO40
EPI0S14		AD14	AD14	AD14	AD14	PG1_GPIO41
EPI0S15		AD15	AD15	AD15	AD15	PF5_GPIO37
EPI0S16		A16	A16	A16	A16	PJ0_GPIO56
EPI0S17		A17	A17	A17	A17	PJ1_GPIO57
EPI0S18		A18	A18	A18	A18	PJ2_GPIO58
EPI0S19		A19	A19	A19	A19	PD4_GPIO20	PJ3_GPIO59
EPI0S20		A20	A20	A20	A20	PD2_GPIO18
EPI0S21		A21	A21	A21	A21	PD3_GPIO19
EPI0S22		A22	A22	A22	A22	PB5_GPIO13
EPI0S23		A23	A23	A23	A23	PB4_GPIO12
EPI0S24		A24	A24	A24	A24	PE2_GPIO26
EPI0S25		A25	A25	A25	A25	PE3_GPIO27
EPI0S26		A26	A26	A26	CS0	PH6_GPIO54
EPI0S27		A27	A27	CS1	CS1	PH7_GPIO55
EPI0S30		ALE	CS0	CS0	ALE	PD7_GPIO23	PJ6_GPIO62
EPI0S29		WR	WR	WR	WR	PD6_GPIO22	PJ5_GPIO61
EPI0S28		RD	RD	RD	RD	PD5_GPIO21	PJ4_GPIO60
EPI0S31		x	x	x	x	PG7_GPIO47
EPI0S32		x	x	x	x	PF2_GPIO34	PC0_GPIO64
EPI0S33		x	x	x	x	PF3_GPIO35	PC1_GPIO65
EPI0S34		x	x	x	x	PE4_GPIO28
EPI0S35		x	x	x	x	PE5_GPIO29
EPI0S36		x	x	x	x	PB7_GPIO15	PC3_GPIO67
EPI0S37		x	x	x	x	PB6_GPIO14	PC2_GPIO66
EPI0S38		x	x	x	x	PF6_GPIO38	PE4_GPIO28
EPI0S39		x	x	x	x	PG2_GPIO42
EPI0S40		x	x	x	x	PG5_GPIO45
EPI0S41		x	x	x	x	PG6_GPIO46
EPI0S42		x	x	x	x	PN6_GPIO102
EPI0S43		x	x	x	x	PN7_GPIO103

Table 5-45 EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3)

EPI PORT NAME		EPI SIGNAL FUNCTION				DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH ADDRESS LATCH ENABLE (CSCFG = 0x0)	WITH ONE CHIP SELECT (CSCFG = 0x1)	WITH TWO CHIP SELECTS (CSCFG = 0x2)	WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		AD0	AD0	AD0	AD0	PH3_GPIO51
EPI0S1		AD1	AD1	AD1	AD1	PH2_GPIO50
EPI0S2		AD2	AD2	AD2	AD2	PC4_GPIO68
EPI0S3		AD3	AD3	AD3	AD3	PC5_GPIO69
EPI0S4		AD4	AD4	AD4	AD4	PC6_GPIO70
EPI0S5		AD5	AD5	AD5	AD5	PC7_GPIO71
EPI0S6		AD6	AD6	AD6	AD6	PH0_GPIO48
EPI0S7		AD7	AD7	AD7	AD7	PH1_GPIO49
EPI0S8		AD8	AD8	AD8	AD8	PE0_GPIO24
EPI0S9		AD9	AD9	AD9	AD9	PE1_GPIO25
EPI0S10		AD10	AD10	AD10	AD10	PH4_GPIO52
EPI0S11		AD11	AD11	AD11	AD11	PH5_GPIO53
EPI0S12		AD12	AD12	AD12	AD12	PF4_GPIO36
EPI0S13		AD13	AD13	AD13	AD13	PG0_GPIO40
EPI0S14		AD14	AD14	AD14	AD14	PG1_GPIO41
EPI0S15		AD15	AD15	AD15	AD15	PF5_GPIO37
EPI0S16		A16	A16	A16	A16	PJ0_GPIO56
EPI0S17		A17	A17	A17	A17	PJ1_GPIO57
EPI0S18		A18	A18	A18	A18	PJ2_GPIO58
EPI0S19		A19	A19	A19	A19	PD4_GPIO20	PJ3_GPIO59
EPI0S20		A20	A20	A20	A20	PD2_GPIO18
EPI0S21		A21	A21	A21	A21	PD3_GPIO19
EPI0S22		A22	A22	A22	A22	PB5_GPIO13
EPI0S23		A23	A23	A23	A23	PB4_GPIO12
EPI0S24		A24	A24	A24	BSEL0	PE2_GPIO26
EPI0S25		A25	A25	BSEL0	BSEL1	PE3_GPIO27
EPI0S26		BSEL0	BSEL0	BSEL1	CS0	PH6_GPIO54
EPI0S27		BSEL1	BSEL1	CS1	CS1	PH7_GPIO55
EPI0S30		ALE	CS0	CS0	ALE	PD7_GPIO23	PJ6_GPIO62
EPI0S29		WR	WR	WR	WR	PD6_GPIO22	PJ5_GPIO61
EPI0S28		RD	RD	RD	RD	PD5_GPIO21	PJ4_GPIO60
EPI0S31		x	x	x	x	PG7_GPIO47
EPI0S32		x	x	x	x	PF2_GPIO34	PC0_GPIO64
EPI0S33		x	x	x	x	PF3_GPIO35	PC1_GPIO65
EPI0S34		x	x	x	x	PE4_GPIO28
EPI0S35		x	x	x	x	PE5_GPIO29
EPI0S36		x	x	x	x	PB7_GPIO15	PC3_GPIO67
EPI0S37		x	x	x	x	PB6_GPIO14	PC2_GPIO66
EPI0S38		x	x	x	x	PF6_GPIO38	PE4_GPIO28
EPI0S39		x	x	x	x	PG2_GPIO42
EPI0S40		x	x	x	x	PG5_GPIO45
EPI0S41		x	x	x	x	PG6_GPIO46
EPI0S42		x	x	x	x	PN6_GPIO102
EPI0S43		x	x	x	x	PN7_GPIO103

5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode

The HB-16 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-16 Non-Muxed Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (chip select) signals to enable one of four external peripherals; and two BSEL (byte select) signals to accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For Non-Muxed bus cycles, most of the CSCFG modes also support a RDY signal. The RDY input to EPI is used by an external peripheral to extend bus cycles when the peripheral needs more time to complete reading or writing of data. While most EPI modes use up to 32 pins, the Non-Muxed CSCFG modes with 3 and 4 Chip Selects use 12 additional pins to extend the address reach and the number of CS signals. For detailed maps of HB-16 Non-Muxed Modes without Byte Selects, see Table 5-46 and Table 5-47. For detailed maps of HB-16 Non-Muxed Modes with Byte Selects, see Table 5-48 and Table 5-49.

Table 5-46 EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)

EPI PORT NAME		EPI SIGNAL FUNCTION				DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH ADDRESS LATCH ENABLE (CSCFG = 0x0)	WITH ONE CHIP SELECT (CSCFG = 0x1)	WITH TWO CHIP SELECTS (CSCFG = 0x2)	WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		D0	D0	D0	D0	PH3_GPIO51
EPI0S1		D1	D1	D1	D1	PH2_GPIO50
EPI0S2		D2	D2	D2	D2	PC4_GPIO68
EPI0S3		D3	D3	D3	D3	PC5_GPIO69
EPI0S4		D4	D4	D4	D4	PC6_GPIO70
EPI0S5		D5	D5	D5	D5	PC7_GPIO71
EPI0S6		D6	D6	D6	D6	PH0_GPIO48
EPI0S7		D7	D7	D7	D7	PH1_GPIO49
EPI0S8		D8	D8	D8	D8	PE0_GPIO24
EPI0S9		D9	D9	D9	D9	PE1_GPIO25
EPI0S10		D10	D10	D10	D10	PH4_GPIO52
EPI0S11		D11	D11	D11	D11	PH5_GPIO53
EPI0S12		D12	D12	D12	D12	PF4_GPIO36
EPI0S13		D13	D13	D13	D13	PG0_GPIO40
EPI0S14		D14	D14	D14	D14	PG1_GPIO41
EPI0S15		D15	D15	D15	D15	PF5_GPIO37
EPI0S16		A0	A0	A0	A0	PJ0_GPIO56
EPI0S17		A1	A1	A1	A1	PJ1_GPIO57
EPI0S18		A2	A2	A2	A2	PJ2_GPIO58
EPI0S19		A3	A3	A3	A3	PD4_GPIO20	PJ3_GPIO59
EPI0S20		A4	A4	A4	A4	PD2_GPIO18
EPI0S21		A5	A5	A5	A5	PD3_GPIO19
EPI0S22		A6	A6	A6	A6	PB5_GPIO13
EPI0S23		A7	A7	A7	A7	PB4_GPIO12
EPI0S24		A8	A8	A8	A8	PE2_GPIO26
EPI0S25		A9	A9	A9	A9	PE3_GPIO27
EPI0S26		A10	A10	A10	CS0	PH6_GPIO54
EPI0S27		A11	A11	CS1	CS1	PH7_GPIO55
EPI0S30		ALE	CS0	CS0	ALE	PD7_GPIO23	PJ6_GPIO62
EPI0S29		WR	WR	WR	WR	PD6_GPIO22	PJ5_GPIO61
EPI0S28		RD	RD	RD	RD	PD5_GPIO21	PJ4_GPIO60
EPI0S32		x	RDY	RDY	RDY	PF2_GPIO34	PC0_GPIO64
EPI0S31		x	x	x	x	PG7_GPIO47
EPI0S33		x	x	x	x	PF3_GPIO35	PC1_GPIO65
EPI0S34		x	x	x	x	PE4_GPIO28
EPI0S35		x	x	x	x	PE5_GPIO29
EPI0S36		x	x	x	x	PB7_GPIO15	PC3_GPIO67
EPI0S37		x	x	x	x	PB6_GPIO14	PC2_GPIO66
EPI0S38		x	x	x	x	PF6_GPIO38	PE4_GPIO28
EPI0S39		x	x	x	x	PG2_GPIO42
EPI0S40		x	x	x	x	PG5_GPIO45
EPI0S41		x	x	x	x	PG6_GPIO46
EPI0S42		x	x	x	x	PN6_GPIO102
EPI0S43		x	x	x	x	PN7_GPIO103

Table 5-47 EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE=0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)

EPI PORT NAME		EPI SIGNAL FUNCTION	DEVICE PIN			EPI PORT NAME		EPI SIGNAL FUNCTION	DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH THREE CHIP SELECTS (CSCFG = 0x7)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)			ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH FOUR CHIP SELECTS (CSCFG = 0x5)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		D0	PH3_GPIO51			EPI0S0		D0	PH3_GPIO51
EPI0S1		D1	PH2_GPIO50			EPI0S1		D1	PH2_GPIO50
EPI0S2		D2	PC4_GPIO68			EPI0S2		D2	PC4_GPIO68
EPI0S3		D3	PC5_GPIO69			EPI0S3		D3	PC5_GPIO69
EPI0S4		D4	PC6_GPIO70			EPI0S4		D4	PC6_GPIO70
EPI0S5		D5	PC7_GPIO71			EPI0S5		D5	PC7_GPIO71
EPI0S6		D6	PH0_GPIO48			EPI0S6		D6	PH0_GPIO48
EPI0S7		D7	PH1_GPIO49			EPI0S7		D7	PH1_GPIO49
EPI0S8		D8	PE0_GPIO24			EPI0S8		D8	PE0_GPIO24
EPI0S9		D9	PE1_GPIO25			EPI0S9		D9	PE1_GPIO25
EPI0S10		D10	PH4_GPIO52			EPI0S10		D10	PH4_GPIO52
EPI0S11		D11	PH5_GPIO53			EPI0S11		D11	PH5_GPIO53
EPI0S12		D12	PF4_GPIO36			EPI0S12		D12	PF4_GPIO36
EPI0S13		D13	PG0_GPIO40			EPI0S13		D13	PG0_GPIO40
EPI0S14		D14	PG1_GPIO41			EPI0S14		D14	PG1_GPIO41
EPI0S15		D15	PF5_GPIO37			EPI0S15		D15	PF5_GPIO37
EPI0S16		A0	PJ0_GPIO56			EPI0S16		A0	PJ0_GPIO56
EPI0S17		A1	PJ1_GPIO57			EPI0S17		A1	PJ1_GPIO57
EPI0S18		A2	PJ2_GPIO58			EPI0S18		A2	PJ2_GPIO58
EPI0S19		A3	PD4_GPIO20	PJ3_GPIO59		EPI0S19		A3	PD4_GPIO20	PJ3_GPIO59
EPI0S20		A4	PD2_GPIO18			EPI0S20		A4	PD2_GPIO18
EPI0S21		A5	PD3_GPIO19			EPI0S21		A5	PD3_GPIO19
EPI0S22		A6	PB5_GPIO13			EPI0S22		A6	PB5_GPIO13
EPI0S23		A7	PB4_GPIO12			EPI0S23		A7	PB4_GPIO12
EPI0S24		A8	PE2_GPIO26			EPI0S24		A8	PE2_GPIO26
EPI0S25		A9	PE3_GPIO27			EPI0S25		A9	PE3_GPIO27
EPI0S26		A10	PH6_GPIO54			EPI0S26		A10	PH6_GPIO54
EPI0S36		A11	PB7_GPIO15	PC3_GPIO67		EPI0S36		A11	PB7_GPIO15	PC3_GPIO67
EPI0S37		A12	PB6_GPIO14	PC2_GPIO66		EPI0S37		A12	PB6_GPIO14	PC2_GPIO66
EPI0S38		A13	PF6_GPIO38	PE4_GPIO28		EPI0S38		A13	PF6_GPIO38	PE4_GPIO28
EPI0S39		A14	PG2_GPIO42			EPI0S39		A14	PG2_GPIO42
EPI0S27		A15	PH7_GPIO55			EPI0S40		A15	PG5_GPIO45
EPI0S35		A16	PE5_GPIO29			EPI0S41		A16	PG6_GPIO46
EPI0S40		A17	PG5_GPIO45			EPI0S42		A17	PN6_GPIO102
EPI0S41		A18	PG6_GPIO46			EPI0S43		A18	PN7_GPIO103
EPI0S42		A19	PN6_GPIO102			EPI0S30		CS0	PD7_GPIO23	PJ6_GPIO62
EPI0S43		A20	PN7_GPIO103			EPI0S27		CS1	PH7_GPIO55
EPI0S30		CS0	PD7_GPIO23	PJ6_GPIO62		EPI0S34		CS2	PE4_GPIO28
EPI0S34		CS2	PE4_GPIO28			EPI0S33		CS3	PF3_GPIO35	PC1_GPIO65
EPI0S33		CS3	PF3_GPIO35	PC1_GPIO65
						EPI0S29		WR	PD6_GPIO22	PJ5_GPIO61
EPI0S29		WR	PD6_GPIO22	PJ5_GPIO61		EPI0S28		RD	PD5_GPIO21	PJ4_GPIO60
EPI0S28		RD	PD5_GPIO21	PJ4_GPIO60		EPI0S32		RDY	PF2_GPIO34	PC0_GPIO64
EPI0S32		RDY	PF2_GPIO34	PC0_GPIO64
						EPI0S31		x	PG7_GPIO47
EPI0S31		x	PG7_GPIO47			EPI0S35		x	PE5_GPIO29

Table 5-48 EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)

EPI PORT NAME		EPI SIGNAL FUNCTION				DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH ADDRESS LATCH ENABLE (CSCFG = 0x0)	WITH ONE CHIP SELECT (CSCFG = 0x1)	WITH TWO CHIP SELECTS (CSCFG = 0x2)	WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		D0	D0	D0	D0	PH3_GPIO51
EPI0S1		D1	D1	D1	D1	PH2_GPIO50
EPI0S2		D2	D2	D2	D2	PC4_GPIO68
EPI0S3		D3	D3	D3	D3	PC5_GPIO69
EPI0S4		D4	D4	D4	D4	PC6_GPIO70
EPI0S5		D5	D5	D5	D5	PC7_GPIO71
EPI0S6		D6	D6	D6	D6	PH0_GPIO48
EPI0S7		D7	D7	D7	D7	PH1_GPIO49
EPI0S8		D8	D8	D8	D8	PE0_GPIO24
EPI0S9		D9	D9	D9	D9	PE1_GPIO25
EPI0S10		D10	D10	D10	D10	PH4_GPIO52
EPI0S11		D11	D11	D11	D11	PH5_GPIO53
EPI0S12		D12	D12	D12	D12	PF4_GPIO36
EPI0S13		D13	D13	D13	D13	PG0_GPIO40
EPI0S14		D14	D14	D14	D14	PG1_GPIO41
EPI0S15		D15	D15	D15	D15	PF5_GPIO37
EPI0S16		A0	A0	A0	A0	PJ0_GPIO56
EPI0S17		A1	A1	A1	A1	PJ1_GPIO57
EPI0S18		A2	A2	A2	A2	PJ2_GPIO58
EPI0S19		A3	A3	A3	A3	PD4_GPIO20	PJ3_GPIO59
EPI0S20		A4	A4	A4	A4	PD2_GPIO18
EPI0S21		A5	A5	A5	A5	PD3_GPIO19
EPI0S22		A6	A6	A6	A6	PB5_GPIO13
EPI0S23		A7	A7	A7	A7	PB4_GPIO12
EPI0S24		A8	A8	A8	BSEL0	PE2_GPIO26
EPI0S25		A9	A9	BSEL0	BSEL1	PE3_GPIO27
EPI0S26		BSEL0	BSEL0	BSEL1	CS0	PH6_GPIO54
EPI0S27		BSEL1	BSEL1	CS1	CS1	PH7_GPIO55
EPI0S30		ALE	CS0	CS0	ALE	PD7_GPIO23	PJ6_GPIO62
EPI0S29		WR	WR	WR	WR	PD6_GPIO22	PJ5_GPIO61
EPI0S28		RD	RD	RD	RD	PD5_GPIO21	PJ4_GPIO60
EPI0S32		x	RDY	RDY	RDY	PF2_GPIO34	PC0_GPIO64
EPI0S31		x	x	x	x	PG7_GPIO47
EPI0S33		x	x	x	x	PF3_GPIO35	PC1_GPIO65
EPI0S34		x	x	x	x	PE4_GPIO28
EPI0S35		x	x	x	x	PE5_GPIO29
EPI0S36		x	x	x	x	PB7_GPIO15	PC3_GPIO67
EPI0S37		x	x	x	x	PB6_GPIO14	PC2_GPIO66
EPI0S38		x	x	x	x	PF6_GPIO38	PE4_GPIO28
EPI0S39		x	x	x	x	PG2_GPIO42
EPI0S40		x	x	x	x	PG5_GPIO45
EPI0S41		x	x	x	x	PG6_GPIO46
EPI0S42		x	x	x	x	PN6_GPIO102
EPI0S43		x	x	x	x	PN7_GPIO103

Table 5-49 EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)

EPI PORT NAME		EPI SIGNAL FUNCTION	DEVICE PIN			EPI PORT NAME		EPI SIGNAL FUNCTION	DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH THREE CHIP SELECTS (CSCFG = 0x7)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)			ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH FOUR CHIP SELECTS (CSCFG = 0x5)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		D0	PH3_GPIO51			EPI0S0		D0	PH3_GPIO51
EPI0S1		D1	PH2_GPIO50			EPI0S1		D1	PH2_GPIO50
EPI0S2		D2	PC4_GPIO68			EPI0S2		D2	PC4_GPIO68
EPI0S3		D3	PC5_GPIO69			EPI0S3		D3	PC5_GPIO69
EPI0S4		D4	PC6_GPIO70			EPI0S4		D4	PC6_GPIO70
EPI0S5		D5	PC7_GPIO71			EPI0S5		D5	PC7_GPIO71
EPI0S6		D6	PH0_GPIO48			EPI0S6		D6	PH0_GPIO48
EPI0S7		D7	PH1_GPIO49			EPI0S7		D7	PH1_GPIO49
EPI0S8		D8	PE0_GPIO24			EPI0S8		D8	PE0_GPIO24
EPI0S9		D9	PE1_GPIO25			EPI0S9		D9	PE1_GPIO25
EPI0S10		D10	PH4_GPIO52			EPI0S10		D10	PH4_GPIO52
EPI0S11		D11	PH5_GPIO53			EPI0S11		D11	PH5_GPIO53
EPI0S12		D12	PF4_GPIO36			EPI0S12		D12	PF4_GPIO36
EPI0S13		D13	PG0_GPIO40			EPI0S13		D13	PG0_GPIO40
EPI0S14		D14	PG1_GPIO41			EPI0S14		D14	PG1_GPIO41
EPI0S15		D15	PF5_GPIO37			EPI0S15		D15	PF5_GPIO37
EPI0S16		A0	PJ0_GPIO56			EPI0S16		A0	PJ0_GPIO56
EPI0S17		A1	PJ1_GPIO57			EPI0S17		A1	PJ1_GPIO57
EPI0S18		A2	PJ2_GPIO58			EPI0S18		A2	PJ2_GPIO58
EPI0S19		A3	PD4_GPIO20	PJ3_GPIO59		EPI0S19		A3	PD4_GPIO20	PJ3_GPIO59
EPI0S20		A4	PD2_GPIO18			EPI0S20		A4	PD2_GPIO18
EPI0S21		A5	PD3_GPIO19			EPI0S21		A5	PD3_GPIO19
EPI0S22		A6	PB5_GPIO13			EPI0S22		A6	PB5_GPIO13
EPI0S23		A7	PB4_GPIO12			EPI0S23		A7	PB4_GPIO12
EPI0S24		A8	PE2_GPIO26			EPI0S24		A8	PE2_GPIO26
EPI0S40		A9	PG5_GPIO45			EPI0S40		A9	PG5_GPIO45
EPI0S41		A10	PG6_GPIO46			EPI0S41		A10	PG6_GPIO46
EPI0S36		A11	PB7_GPIO15	PC3_GPIO67		EPI0S36		A11	PB7_GPIO15	PC3_GPIO67
EPI0S37		A12	PB6_GPIO14	PC2_GPIO66		EPI0S37		A12	PB6_GPIO14	PC2_GPIO66
EPI0S38		A13	PF6_GPIO38	PE4_GPIO28		EPI0S38		A13	PF6_GPIO38	PE4_GPIO28
EPI0S39		A14	PG2_GPIO42			EPI0S39		A14	PG2_GPIO42
EPI0S27		A15	PH7_GPIO55			EPI0S42		A15	PN6_GPIO102
EPI0S35		A16	PE5_GPIO29			EPI0S43		A16	PN7_GPIO103
EPI0S42		A17	PN6_GPIO102			EPI0S25		BSEL0	PE3_GPIO27
EPI0S43		A18	PN7_GPIO103			EPI0S26		BSEL1	PH6_GPIO54
EPI0S25		BSEL0	PE3_GPIO27			EPI0S30		CS0	PD7_GPIO23	PJ6_GPIO62
EPI0S26		BSEL1	PH6_GPIO54			EPI0S27		CS1	PH7_GPIO55
EPI0S30		CS0	PD7_GPIO23	PJ6_GPIO62		EPI0S34		CS2	PE4_GPIO28
EPI0S34		CS2	PE4_GPIO28			EPI0S33		CS3	PF3_GPIO35	PC1_GPIO65
EPI0S33		CS3	PF3_GPIO35	PC1_GPIO65
						EPI0S29		WR	PD6_GPIO22	PJ5_GPIO61
EPI0S29		WR	PD6_GPIO22	PJ5_GPIO61		EPI0S28		RD	PD5_GPIO21	PJ4_GPIO60
EPI0S28		RD	PD5_GPIO21	PJ4_GPIO60		EPI0S32		RDY	PF2_GPIO34	PC0_GPIO64
EPI0S32		RDY	PF2_GPIO34	PC0_GPIO64
						EPI0S31		x	PG7_GPIO47
EPI0S31		x	PG7_GPIO47			EPI0S35		x	PE5_GPIO29

5.10.4.3.2.3 HB-16 FIFO Mode

The HB-16 FIFO Mode uses 16 bits of data, removes ALE and address pins, and optionally adds external FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configuration (FIFO through block RAM). This FIFO Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA accesses. For detailed maps of the HB-16 FIFO Mode, see Table 5-50.

Table 5-50 EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
FIFO Mode (EPIHB16CFG/MODE = 0x3)

EPI PORT NAME		EPI SIGNAL FUNCTION		DEVICE PIN
ACCESSIBLE BY Cortex-M3	ACCESSIBLE BY C28x	WITH ONE CHIP SELECT (CSCFG = 0x1)	WITH TWO CHIP SELECTS (CSCFG = 0x2)	(AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI)
EPI0S0		D0	D0	PH3_GPIO51
EPI0S1		D1	D1	PH2_GPIO50
EPI0S2		D2	D2	PC4_GPIO68
EPI0S3		D3	D3	PC5_GPIO69
EPI0S4		D4	D4	PC6_GPIO70
EPI0S5		D5	D5	PC7_GPIO71
EPI0S6		D6	D6	PH0_GPIO48
EPI0S7		D7	D7	PH1_GPIO49
EPI0S8		D8	D8	PE0_GPIO24
EPI0S9		D9	D9	PE1_GPIO25
EPI0S10		D10	D10	PH4_GPIO52
EPI0S11		D11	D11	PH5_GPIO53
EPI0S12		D12	D12	PF4_GPIO36
EPI0S13		D13	D13	PG0_GPIO40
EPI0S14		D14	D14	PG1_GPIO41
EPI0S15		D15	D15	PF5_GPIO37
EPI0S25		x	CS1	PE3_GPIO27
EPI0S30		CS0	CS0	PD7_GPIO23	PJ6_GPIO62
EPI0S27		FFULL	FFULL	PH7_GPIO55
EPI0S26		FEMPTY	FEMPTY	PH6_GPIO54
EPI0S29		WR	WR	PD6_GPIO22	PJ5_GPIO61
EPI0S28		RD	RD	PD5_GPIO21	PJ4_GPIO60
EPI0S32		x	x	PF2_GPIO34	PC0_GPIO64
EPI0S16		x	x	PJ0_GPIO56
EPI0S17		x	x	PJ1_GPIO57
EPI0S18		x	x	PJ2_GPIO58
EPI0S19		x	x	PD4_GPIO20	PJ3_GPIO59
EPI0S20		x	x	PD2_GPIO18
EPI0S21		x	x	PD3_GPIO19
EPI0S22		x	x	PB5_GPIO13
EPI0S23		x	x	PB4_GPIO12
EPI0S24		x	x	PE2_GPIO26
EPI0S31		x	x	PG7_GPIO47
EPI0S33		x	x	PF3_GPIO35	PC1_GPIO65
EPI0S34		x	x	PE4_GPIO28
EPI0S35		x	x	PE5_GPIO29
EPI0S36		x	x	PB7_GPIO15	PC3_GPIO67
EPI0S37		x	x	PB6_GPIO14	PC2_GPIO66
EPI0S38		x	x	PF6_GPIO38	PE4_GPIO28
EPI0S39		x	x	PG2_GPIO42
EPI0S40		x	x	PG5_GPIO45
EPI0S41		x	x	PG6_GPIO46
EPI0S42		x	x	PN6_GPIO102
EPI0S43		x	x	PN7_GPIO103