ZHCSG57B March   2017  – December 2018 DRV8702D-Q1 , DRV8703D-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
        1. 7.3.1.1 Logic Tables
      2. 7.3.2  MODE Pin
      3. 7.3.3  nFAULT Pin
      4. 7.3.4  Current Regulation
      5. 7.3.5  Amplifier Output (SO)
        1. 7.3.5.1 SO Sample and Hold Operation
      6. 7.3.6  PWM Motor Gate Drivers
        1. 7.3.6.1 Miller Charge (QGD)
      7. 7.3.7  IDRIVE Pin (DRV8702D-Q1 Only)
      8. 7.3.8  Dead Time
      9. 7.3.9  Propagation Delay
      10. 7.3.10 Overcurrent VDS Monitor
      11. 7.3.11 VDS Pin (DRV8702D-Q1 Only)
      12. 7.3.12 Charge Pump
      13. 7.3.13 Gate Drive Clamp
      14. 7.3.14 Protection Circuits
        1. 7.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 7.3.14.2 Logic Undervoltage (UVLO1)
        3. 7.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 7.3.14.4 Overcurrent Protection (OCP)
        5. 7.3.14.5 Gate Driver Fault (GDF)
        6. 7.3.14.6 Thermal Shutdown (TSD)
        7. 7.3.14.7 Watchdog Fault (WDFLT, DRV8703D-Q1 Only)
        8. 7.3.14.8 Reverse Supply Protection
      15. 7.3.15 Hardware Interface
        1. 7.3.15.1 IDRIVE (6-level input)
        2. 7.3.15.2 VDS (6-Level Input)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Serial Peripheral Interface (SPI)
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 DRV8703D-Q1 Memory Map
      2. 7.6.2 Status Registers
        1. 7.6.2.1 FAULT Status Register (address = 0x00h)
          1. Table 15. FAULT Status Field Descriptions
        2. 7.6.2.2 VDS and GDF Status Register Name (address = 0x01h)
          1. Table 16. VDS and GDF Status Field Descriptions
      3. 7.6.3 Control Registers
        1. 7.6.3.1 Main Control Register Name (address = 0x02h)
          1. Table 18. Main Control Field Descriptions
        2. 7.6.3.2 IDRIVE and WD Control Register Name (address = 0x03h)
          1. Table 19. IDRIVE and WD Field Descriptions
        3. 7.6.3.3 VDS Control Register Name (address = 0x04h)
          1. Table 21. VDS Control Field Descriptions
        4. 7.6.3.4 Config Control Register Name (address = 0x05h)
          1. Table 22. Config Control Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 相关链接
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RHB|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DRV8702D-Q1 RHB Package With Wettable Flanks
32-Pin VQFN
Top View
DRV8703D-Q1 RHB Package With Wettable Flanks
32-Pin VQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8702D-Q1 DRV8703D-Q1
AVDD 14 14 PWR Analog regulator. This pin is the 5-V analog supply regulator. Bypass this pin to ground with a 6.3-V, 1-µF ceramic capacitor.
CPH 30 30 PWR Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the supply voltage (VM) between the CPH and CPL pins.
CPL 31 31 PWR Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the supply voltage (VM) between the CPH and CPL pins.
DVDD 12 12 PWR Logic regulator. This pin is the regulator for the 3.3-V logic supply. Bypass this pin to ground with a 6.3-V, 1-µF ceramic capacitor.
GH 18 18 O High-side gate. Connect this pin to the high-side FET gate.
GL 20 20 O Low-side gate. Connect this pin to the low-side FET gate.
GND 1 1 PWR Device ground. Connect this pin to the system ground.
GND 13 13 PWR Device ground. Connect this pin to the system ground.
GND 17 17 PWR Device ground. Connect this pin to the system ground.
GND 25 25 PWR Device ground. Connect this pin to the system ground.
GND 4 — PWR Device ground. Connect this pin to the system ground.
GND 7 — PWR Device ground. Connect this pin to the system ground.
GND 9 — PWR Device ground. Connect this pin to the system ground.
IDRIVE 5 — I Current setting pin for the gate drive. The resistor value or voltage forced on this pin sets the gate-drive current. For more information see the IDRIVE Configuration section.
IN1 2 2 I Input control pins. The logic of this pin is dependent on the MODE pin. This pin is connected to an internal pulldown resistor.
IN2 3 3 I Input control pins. The logic of this pin is dependent on the MODE pin. This pin is connected to an internal pulldown resistor.
MODE 11 11 I Mode control pin. Pull this pin to logic high for half-bridge operation without internal current regulation. Leave this pin as no-connect for half-bridge operation with internal current regulation. Operation of this pin is latched on power up or when exiting sleep mode. This pin is connected to an internal pullup and pulldown resistor.
NC 32 32 NC No connect. No internal connection
nFAULT 10 10 OD Fault indication pin. This pin is pulled logic low when a fault condition occurs. This pin is an open-drain output that requires an external pullup resistor.
nSCS — 5 I SPI chip select. This pin is the select and enable for SPI. This pin is active low. This pin is connected to an internal pulldown resistor.
nSLEEP 8 8 I Device sleep mode. Pull this pin to logic low to put device into a low-power sleep mode with the FETs in high impedance (Hi-Z). This pin is connected to an internal pulldown resistor.
nWDFLT — 9 OD Watchdog fault indication pin. This pin is pulled logic low when a watchdog fault condition occurs. This pin is an open-drain output that requires an external pullup resistor.
RSVD 26 26 RSVD Reserved. Do not connect anything.
RSVD 24 24 RSVD Reserved. Do not connect anything.
SCLK — 7 I SPI clock. This pin is for the SPI clock signal. This pin is connected to an internal pulldown resistor.
SDI — 6 I SPI input. This pin is for the SPI input signal. This pin is connected to an internal pulldown resistor.
SDO — 4 OD SPI output. This pin is for the SPI output signal. This pin is an open-drain output that requires an external pullup resistor.
SH 19 19 I High-side source. Connect this pin to the high-side FET source.
SN 22 22 I Shunt-amplifier negative input. Connect this pin to the current-sense resistor.
SO 16 16 O Shunt-amplifier output. The voltage on this pin is equal to the SP voltage times AV plus an offset. Place no more than 1 nF of capacitance on this pin.
SP 21 21 I Shunt-amplifier positive input. Connect this pin to the current-sense resistor.
SP 23 23 I Shunt-amplifier positive input. Connect this pin to the current-sense resistor.
VCP 29 29 PWR Charge-pump output. Connect a 16-V, 1-µF ceramic capacitor between this pin and the VM pin.
VDRAIN 27 27 I High-side FET drain connection. This pin is common for the half-bridge.
VDS 6 — I VDS monitor setting pin. The resistor value or voltage forced on this pin sets the VDS monitor threshold. For more information see the VDS Configuration section.
VM 28 28 PWR Power supply. Connect this pin to the motor supply voltage. Bypass this pin to ground with a 0.1-µF ceramic plus a 10-µF (minimum) capacitor.
VREF 15 15 I Current set reference input. The voltage on this pin sets the driver chopping current.
(1) I = input, O = output, PWR = power, NC = no connect, OD = open-drain output