7.3.8.1 Fault and Warning Classification

The DRV8305-Q1 integrates extensive error detection and monitoring features. These features allow the design of a robust system that can protect against a variety of system related failure modes. The DRV8305-Q1 classifies error events into two categories and takes different device actions dependent on the error classification.

The first error class is a Warning. There are several types of conditions that are classified as warning only. Warning errors are report only and the DRV8305-Q1 will take no other action effecting the gate drivers or other blocks. When a warning condition occurs it will be reported in the corresponding SPI status register bit and on the nFAULT pin with a repeating 56-µs pulse low followed by a 56-µs pulse high. A warning error can be cleared by an SPI read to the corresponding status register bit. The same warning will not be reported through the nFAULT pin again unless that warning or condition passes and then reoccurs.

• A warning error is reported on the nFAULT pin with a repeating 56-µs pulse low followed by a 56-µs pulse high.
• The warning is reported on the nFAULT pin until a SPI read to the corresponding status register.
• The SPI read will clear the nFAULT report, but the SPI register will remain asserted until the condition has passed.
• The nFAULT pin will report a new warning if the condition clears and then occurs again.

The second error class is a Fault. Fault errors will trigger a shutdown of the gate driver with its major blocks and are reported by holding nFAULT low with the corresponding status register asserted. Fault errors are latched until the appropriate recovery sequence is performed.

• A fault error is reported by holding the nFAULT pin low and asserting the FAULT bit in register 0x1.
• The error type will also be asserted in the SPI registers.
• A fault error is a latched fault and must be cleared with the appropriate recovery sequence.
• If a fault occurs during a warning error, the fault error will take precendence, latch nFAULT low and shutdown the gate driver.
• The output MOSFETs will be placed into their high impedance state in a fault error event.
• To recover from a fault type error, the condition must be removed and the CLR_FLTs bit asserted in register 0x9, bit D1 or an EN_GATE reset pulse issued.
• The CLR_FLTS bit self clears to 0 after fault status reset and nFAULT pin is released.

There are two exceptions to the fault and warning error classes. The first exception is the temperature flag warnings (TEMP_FLAGX). A Temperature Flag warning will not trigger any action on the nFAULT pin and the corresponding status bit will be updated in real time. See the overtemperature section for additional information. The second exception is the MCU Watchdog and VREG Undervoltage (VREG_UV) faults. These are reported on the PWRGD pin to protect the system from lock out and brownout conditions. See their corresponding sections for additional information.

Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.