The DRV7163A device simplifies the design of high-power-density PCBs by eliminating the need for underfill while maintaining required creepage and clearance distances. The device provides tightly matched propagation delays between the high-side and low-side gate drivers, enabling precise dead-time control, a factor that is critical in achieving high efficiency in GaN FET-based applications. Both HI and LI inputs are independently controllable to minimize third-quadrant conduction time. The propagation delay mismatch between the HI and LI channels, for both rising and falling edges, is typically 2ns, allowing extremely tight dead-time optimization. The device also supports a single PWM input mode with resistor-programmable dead-time adjustment for use with controllers that have limited I/O capability. By co-packaging the GaN FET half-bridge with the driver, the DRV7163A achieves optimized gate-loop inductance, significantly improving performance in hard-switched topologies.

An integrated bootstrap circuit with overvoltage regulation establishes that the high-side gate-to-source voltage (V_GS) remains within the safe operating limit of the GaN FET, eliminating the need for external protection components. The built-in driver includes undervoltage lockout (UVLO) protection on both the GVDD and BOOT–HS rails. When either rail voltage falls below the UVLO threshold, the device ignores HI and LI commands to prevent partial FET turn-on. If GVDD remains above 2.5V and below UVLO threshold, the driver actively pulls both gate driver outputs low. Hysteresis on the UVLO threshold prevents chatter and false triggering due to supply noise or transients

The DRV7163A integrates V_DS-based short-circuit protection for both FETs, along with over-temperature reporting. Additional features include zero-voltage detection (ZVD) which enables dead-time optimization and minimize third-quadrant conduction losses.