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Rating Catalog Architecture Half-bridge, Integrated FET Peak output current (A) 50 RDS(ON) (HS + LS) (Ω) 0.045 VDS (max) (V) 120 Features Integrated GaN FET Operating temperature range (°C) -40 to 175
Rating Catalog Architecture Half-bridge, Integrated FET Peak output current (A) 50 RDS(ON) (HS + LS) (Ω) 0.045 VDS (max) (V) 120 Features Integrated GaN FET Operating temperature range (°C) -40 to 175
UNKNOWN (RAR) 17 See data sheet
  • 100V, Half-bridge GaN Motor Driver power stage with integrated driver supporting 48V systems
  • Low GaN on-state resistance
    • 4.4 mΩ RDS(ON) (per FET) at TA=25°C
  • Enables efficient and high density power conversion
    • High output current capability: 35Arms
    • Supports upto 500 kHz PWM switching frequency
    • Ultra-low propagation delay (20ns typical) and matching (2ns typical)
    • Configurable slew rate of GaN FETs
    • Zero-voltage detection (ZVD) reporting for dead-time optimization.
    • Independent input mode (IIM) control
    • Single PWM input with resistor programmable dead-time option for IO-limited controllers
  • 5V external bias power supply
    • Supports 3.3V and 5V input logic levels
  • Robust protection
    • Interlock protection in Independent Input Mode (IIM)
    • Internal bootstrap supply voltage regulation to prevent GaN FET Overdrive
    • VDS monitoring based cycle-by-cyle short-circuit protection
    • Fault indication for over-temperature, supply under-voltage and short-circuit events
  • Parasitic optimized QFN package with exposed top pad to support top-side cooling.
  • 100V, Half-bridge GaN Motor Driver power stage with integrated driver supporting 48V systems
  • Low GaN on-state resistance
    • 4.4 mΩ RDS(ON) (per FET) at TA=25°C
  • Enables efficient and high density power conversion
    • High output current capability: 35Arms
    • Supports upto 500 kHz PWM switching frequency
    • Ultra-low propagation delay (20ns typical) and matching (2ns typical)
    • Configurable slew rate of GaN FETs
    • Zero-voltage detection (ZVD) reporting for dead-time optimization.
    • Independent input mode (IIM) control
    • Single PWM input with resistor programmable dead-time option for IO-limited controllers
  • 5V external bias power supply
    • Supports 3.3V and 5V input logic levels
  • Robust protection
    • Interlock protection in Independent Input Mode (IIM)
    • Internal bootstrap supply voltage regulation to prevent GaN FET Overdrive
    • VDS monitoring based cycle-by-cyle short-circuit protection
    • Fault indication for over-temperature, supply under-voltage and short-circuit events
  • Parasitic optimized QFN package with exposed top pad to support top-side cooling.

The DRV7163A device is a family of 100V half-bridge power stages, with integrated gate-driver and enhancement-mode gallium nitride (GaN) FETs. The devices consist of a high-frequency GaN FET driver in a half-bridge configuration, that drives two 100V GaN FETs.

GaN FETs provide significant advantages for power conversion as GaN FETs have zero reverse recovery and very small input capacitance (CISS) and output capacitance (COSS). All the devices are mounted on a completely bond-wire free package platform with minimized package parasitic elements, which can be easily mounted on PCBs.

The TTL logic compatible inputs support 3.3V and 5V logic levels, regardless of the GVDD voltage. A proprietary bootstrap voltage control technique regulates the gate voltages of the enhancement mode GaN FETs within the safe operating range. The device extends advantages of discrete GaN FETs by offering a more user-friendly interface. The device is an excellent option for applications requiring high-frequency, high-efficiency operation in a small form factor.

The DRV7163A device is a family of 100V half-bridge power stages, with integrated gate-driver and enhancement-mode gallium nitride (GaN) FETs. The devices consist of a high-frequency GaN FET driver in a half-bridge configuration, that drives two 100V GaN FETs.

GaN FETs provide significant advantages for power conversion as GaN FETs have zero reverse recovery and very small input capacitance (CISS) and output capacitance (COSS). All the devices are mounted on a completely bond-wire free package platform with minimized package parasitic elements, which can be easily mounted on PCBs.

The TTL logic compatible inputs support 3.3V and 5V logic levels, regardless of the GVDD voltage. A proprietary bootstrap voltage control technique regulates the gate voltages of the enhancement mode GaN FETs within the safe operating range. The device extends advantages of discrete GaN FETs by offering a more user-friendly interface. The device is an excellent option for applications requiring high-frequency, high-efficiency operation in a small form factor.

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* 数据表 DRV7163A 100V GaN Half-Bridge Power Stage 数据表 PDF | HTML 2026年 7月 24日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日

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UNKNOWN (RAR) 17 Ultra Librarian

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