ZHCSOV8A October   2021  – January 2022 DLPC3420

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 DSI Host Timing Requirements
    16. 6.16 Flash Interface Timing Requirements
    17. 6.17 Other Timing Requirements
    18. 6.18 DMD Sub-LVDS Interface Switching Characteristics
    19. 6.19 DMD Parking Switching Characteristics
    20. 6.20 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 Parallel Interface
          1. 7.3.1.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
        3. 7.3.1.3 DSI Interface
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Test Point Support
      7. 7.3.7 DMD Interface
        1. 7.3.7.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  PLL Power Layout
      2. 10.1.2  Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3  DSI Interface Layout
      4. 10.1.4  Unused Pins
      5. 10.1.5  DMD Control and Sub-LVDS Signals
      6. 10.1.6  Layer Changes
      7. 10.1.7  Stubs
      8. 10.1.8  Terminations
      9. 10.1.9  Routing Vias
      10. 10.1.10 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
      3. 11.1.3 Video Timing Parameter Definitions
    2. 11.2 Related Documentation
    3. 11.3 Related Links
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information
  13. 13Package Option Addendum
    1. 13.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

7.3.7.1 Sub-LVDS (HS) Interface

Internal software selection allows the controller to support multiple DMD interface swap configurations. These options can improve board layout by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 7-8 shows the four options available for the DLP160AP DMD.

Table 7-8 DLP160AP (0.16 QnHD) DMD - Controller to 4-Lane DMD Pin Mapping Options
DLPC3420 Controller 4-LANE DMD ROUTING OPTIONS DMD PINS
Option 1
Swap Control = x0		 Option 2
Swap Control = x2		 Option 3
Swap Control = x1		 Option 4
Swap Control = x3
HS_WDATA_D_P
HS_WDATA_D_N		 HS_WDATA_E_P
HS_WDATA_E_N		 HS_WDATA_H_P
HS_WDATA_H_N		 HS_WDATA_A_P
HS_WDATA_A_N		 Input DATA_p_0
Input DATA_n_0
HS_WDATA_C_P
HS_WDATA_C_N		 HS_WDATA_F_P
HS_WDATA_F_N		 HS_WDATA_G_P
HS_WDATA_G_N		 HS_WDATA_B_P
HS_WDATA_B_N		 Input DATA_p_1
Input DATA_n_1
HS_WDATA_F_P
HS_WDATA_F_N		 HS_WDATA_C_P
HS_WDATA_C_N		 HS_WDATA_B_P
HS_WDATA_B_N		 HS_WDATA_G_P
HS_WDATA_G_N		 Input DATA_p_2
Input DATA_n_2
HS_WDATA_E_P
HS_WDATA_E_N		 HS_WDATA_D_P
HS_WDATA_D_N		 HS_WDATA_A_P
HS_WDATA_A_N		 HS_WDATA_H_P
HS_WDATA_H_N		 Input DATA_p_3
Input DATA_n_3
GUID-20211010-SS0I-T51J-RH7N-N84DMKXKZ29K-low.png Figure 7-9 DLP160AP (0.16 QnHD) DMD Interface Example

The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements.