ZHCSOV8A October   2021  – January 2022 DLPC3420

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 DSI Host Timing Requirements
    16. 6.16 Flash Interface Timing Requirements
    17. 6.17 Other Timing Requirements
    18. 6.18 DMD Sub-LVDS Interface Switching Characteristics
    19. 6.19 DMD Parking Switching Characteristics
    20. 6.20 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 Parallel Interface
          1. 7.3.1.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
        3. 7.3.1.3 DSI Interface
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Test Point Support
      7. 7.3.7 DMD Interface
        1. 7.3.7.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  PLL Power Layout
      2. 10.1.2  Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3  DSI Interface Layout
      4. 10.1.4  Unused Pins
      5. 10.1.5  DMD Control and Sub-LVDS Signals
      6. 10.1.6  Layer Changes
      7. 10.1.7  Stubs
      8. 10.1.8  Terminations
      9. 10.1.9  Routing Vias
      10. 10.1.10 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
      3. 11.1.3 Video Timing Parameter Definitions
    2. 11.2 Related Documentation
    3. 11.3 Related Links
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information
  13. 13Package Option Addendum
    1. 13.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

10.1.2.1 Recommended Crystal Oscillator Configuration

Table 10-1 Crystal Port Characteristics
PARAMETERNOMUNIT
PLL_REFCLK_I TO GND capacitance1.5pF
PLL_REFCLK_O TO GND capacitance1.5pF
Table 10-2 Recommended Crystal Configuration
PARAMETER (1)(2)RECOMMENDEDUNIT
Crystal circuit configurationParallel resonant
Crystal typeFundamental (first harmonic)
Crystal nominal frequency24MHz
Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity)±200PPM
Maximum startup time1.0ms
Crystal equivalent series resistance (ESR)120 (max)Ω
Crystal load6pF
RS drive resistor (nominal)100Ω
RFB feedback resistor (nominal)1MΩ
CL1 external crystal load capacitorSee equation in Figure 10-2 notespF
CL2 external crystal load capacitorSee equation in Figure 10-2 notespF
PCB layoutA ground isolation ring around the crystal is recommended
(1) Temperature range of –30°C to 85°C.
(2) The crystal bias is determined by the controllers VCC_INTF voltage rail, which is variable (not the VCC18 rail).

If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC34xx controller, and the PLL_REFCLK_O pin must be left unconnected.

Table 10-3 Recommended Crystal Parts
MANUFACTURER(1)(2)PART NUMBERSPEED
(MHz)		TEMPERATURE AND AGING
(ppm)		MAXIMUM
ESR (Ω)		LOAD CAPACITANCE
(pF)		PACKAGE DIMENSIONS
(mm)
KDSDSX211G-24.000M-8pF-50-5024±5012082.0 × 1.6
MurataXRCGB24M000F0L11R024±10012062.0 × 1.6
NDKNX2016SA 24M
EXS00A-CS05733		24±14512062.0 × 1.6
(1) The crystal devices in this table have been validated to work with the DLPC34xx controller. Other devices may also be compatible but have not necessarily been validated by TI.
(2) Operating temperature range: –30°C to 85°C for all crystals.