ZHCSOK9A october   2021  – june 2023 DLPA300

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics Control Logic
    6. 6.6  5-V Linear Regulator
    7. 6.7  Bias Voltage Boost Converter
    8. 6.8  Reset Voltage Buck-Boost Converter
    9. 6.9  VOFFSET Regulator
    10. 6.10 Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Linear Regulator
      2. 7.3.2 Bias Voltage Boost Converter
      3. 7.3.3 Reset Voltage Buck-Boost Converter
      4. 7.3.4 VOFFSET Regulator
      5. 7.3.5 Serial Communications Port (SCP)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection Guidelines
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Rail Guidelines
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding Guidelines
    2. 10.2 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 静电放电警告
    8. 11.8 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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7.3.5 Serial Communications Port (SCP)

The SCP is a full duplex, synchronous, character-oriented (byte) port that allows exchange of data between the DLPC4430 or DLPC4420 display controller, and the DLPA300 micromirror driver (and other DLP devices). The display controller is the primary on the SCP bus. The DLPA300 micromirror driver is the secondary on the SCP bus.

Table 7-1 Serial Communications Port Signal Definitions
SIGNALI/OFROM/TOTYPEDESCRIPTION
SCPCKISCP bus primary to secondaryLVTTL compatibleSCP bus serial transfer clock. The host processor (primary) generates this clock.
SCPENISCP bus primary to secondaryLVTTL compatibleSCP bus access enable (low true). When high, secondary resets to the idle state, and SCPDO output is tristated. Pulling SCPEN low initiates a read or write access. SCPEN must remain low for an entire read/write access, and must be pulled high after the last data cycle. To abort a read or write cycle, pull SCPEN high at any point.
SCPDIISCP bus primary to secondaryLVTTL compatibleSCP bus serial data input. Data bits are valid and must be clocked in on the falling edge of SCPCK.
SCPDOOSCP bus secondary to primaryLVTTL, open drain w/tristateSCP bus serial data output. Data bits must clocked out on the rising edge of SCPCK. A 1-kΩ pullup resistor to the 3.3-V display controller supply is required.
IRQOSCP bus secondary to primaryLVTTL, open drainNot part of the SCP bus definition. Asynchronous interrupt signal from secondary to request service from the primary. A 1-kΩ pullup resistor to the 3.3-V display controller supply is required.