The DACx0502 digital interface is programmed to work in I2C mode when the logic level of the SPI2C pin is 1 at power up. In I2C mode, the DACx0502 have a 2-wire serial interface: SCL, SDA, and one address pin, A0. The I2C bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both the SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins SDA and SCL.
The I2C specification states that the device that controls communication is called a master, and the devices that are controlled by the master are called slaves. The master device generates the SCL signal. The master device also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device on an I2C bus is typically a microcontroller or DSP. The DACx0502 operate as a slave device on the I2C bus. A slave device acknowledges master commands, and upon master control, receives or transmits data.
Typically, the DACx0502 operate as a slave receiver. A master device writes to the DACx0502, a slave receiver. However, if a master device requires the DACx0502 internal register data, the DACx0502 operate as a slave transmitter. In this case, the master device reads from the DACx0502 According to I2C terminology, read and write refer to the master device.
The DACx0502 are slave devices that support the following data transfer modes:
The data transfer protocol for standard and fast modes is exactly the same; therefore, these modes are referred to as F/S-mode in this document. The fast-mode plus protocol is supported in terms of data transfer speed, but not output current. The low-level output current would be 3 mA, similar to the case of standard and fast modes. The DACx0502 support 7-bit addressing. The 10-bit addressing mode is not supported. These devices support the general call reset function. Sending the following sequence initiates a software reset within the device: start/repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the falling edge of the ACK bit, following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of the ninth clock cycle as shown in Figure 59.