7.3.2 Dual-Bus Data Interface and Timing

In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5672A consist of two independent, 14-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA, WRTB) and clock (CLKA, CLKB) lines. The WRTA, WRTB lines control the channel input latches and the CLKA, CLKB lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRTA, WRTB line.

The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock domains having equal periods (but possibly different phases) are input to the DAC5672A. The DAC5672A is defined by a minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs. The rising edge of CLKA, CLKB must occur at the same time or before the rising edge of the WRTA, WRTB signal. A minimum delay of 2 ns must be maintained if the rising edge of the clock occurs after the rising edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected externally. Note that all specifications were measured with the WRTA, WRTB and CLKA, CLKB lines connected together.

Figure 17. Dual-Bus Mode Operation