ZHCSBF0D August   2013  – February 2018 DAC3151 , DAC3161 , DAC3171

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     DAC31x1 系统框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions: DAC3151
    2.     Pin Functions: DAC3161
    3.     Pin Functions: DAC3171 7-Bit Interface Mode
    4.     Pin Functions: DAC3171 14-Bit Interface Mode
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC Specifications
    6. 6.6 Electrical Characteristics: AC Specifications
    7. 6.7 Electrical Characteristics: Digital Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Data Input Formats
      2. 7.3.2 Serial Interface
        1. Table 1. Instruction Byte of the Serial interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Synchronization Modes
      2. 7.4.2 Alarm Monitoring
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1  Register Name: config0 – Address: 0x00, Default: 0x4FC
        1. Table 6. Register Name: config0 – Address: 0x00, Default: 0x4FC
      2. 7.6.2  Register Name: config1 – Address: 0x01, Default: 0x600E
        1. Table 7. Register Name: config1 – Address: 0x01, Default: 0x600E
      3. 7.6.3  Register Name: config2 – Address: 0x02, Default: 0x3FFF
        1. Table 8. Register Name: config2 – Address: 0x02, Default: 0x3FFF
      4. 7.6.4  Register Name: config3 – Address: 0x03, Default: 0x0000
        1. Table 9. Register Name: config3 – Address: 0x03, Default: 0x0000
      5. 7.6.5  Register Name: config4 – Address: 0x04, Default: 0x0000
        1. Table 10. Register Name: config4 – Address: 0x04, Default: 0x0000
      6. 7.6.6  Register Name: config5 – Address: 0x05, Default: 0x0000
        1. Table 11. Register Name: config5 – Address: 0x05, Default: 0x0000
      7. 7.6.7  Register Name: config6 – Address: 0x06, Default: 0x0010(DAC3171); 0x0094(DAC3161); 0x0098(DAC3151)
        1. Table 12. Register Name: config6 – Address: 0x06, Default: 0x0010(DAC3171); 0x0094(DAC3161); 0x0098(DAC3151)
      8. 7.6.8  Register Name: config7 – Address: 0x07, Default: 0xFFFF
        1. Table 13. Register Name: config7 – Address: 0x07, Default: 0xFFFF
      9. 7.6.9  Register Name: config8 – Address: 0x08, Default: 0x6000
        1. Table 14. Register Name: config8 – Address: 0x08, Default: 0x6000
      10. 7.6.10 Register Name: config9 – Address: 0x09, Default: 0x8000
        1. Table 15. Register Name: config9 – Address: 0x09, Default: 0x8000
      11. 7.6.11 Register name: config10 – Address: 0x0A, Default: 0xF080
        1. Table 16. Register Name: config10 – Address: 0x0A, Default: 0xF080
      12. 7.6.12 Register Name: config11 – Address: 0x0B, Default: 0x1111
        1. Table 17. Register Name: config11 – Address: 0x0B, Default: 0x1111
      13. 7.6.13 Register Name: config12 – Address: 0x0C, Default: 0x3A7A
        1. Table 18. Register Name: config12 – Address: 0x0C, Default: 0x3A7A
      14. 7.6.14 Register Name: config13 – Address: 0x0D, Default: 0x36B6
        1. Table 19. Register Name: config13 – Address: 0x0D, Default: 0x36B6
      15. 7.6.15 Register Name: config14 – Address: 0x0E, Default: 0x2AEA
        1. Table 20. Register name: config14 – Address: 0x0E, Default: 0x2AEA
      16. 7.6.16 Register name: config15 – Address: 0x0F, Default: 0x0545
        1. Table 21. Register Name: config15 – Address: 0x0F, Default: 0x0545
      17. 7.6.17 Register Name: config16 – Address: 0x10, Default: 0x0585
        1. Table 22. Register Name: config16 – Address: 0x10, Default: 0x0585
      18. 7.6.18 Register Name: config17 – Address: 0x11, Default: 0x0949
        1. Table 23. Register Name: config17 – Address: 0x11, Default: 0x0949
      19. 7.6.19 Register Name: config18 – Address: 0x12, Default: 0x1515
        1. Table 24. Register Name: config18 – Address: 0x12, Default: 0x1515
      20. 7.6.20 Register Name: config19 – Address: 0x13, Default: 0x3ABA
        1. Table 25. Register Name: config19 – Address: 0x13, Default: 0x3ABA
      21. 7.6.21 Register Name: config20– Address: 0x14, Default: 0x0000
        1. Table 26. Register Name: config20– Address: 0x14, Default: 0x0000
      22. 7.6.22 Register Name: config21– Address: 0x15, Default: 0xFFFF
        1. Table 27. Register Name: config21– Address: 0x15, Default: 0xFFFF
      23. 7.6.23 Register Name: config22– Address: 0x16, Default: 0x0000
        1. Table 28. Register Name: config22– Address: 0x16, Default: 0x0000
      24. 7.6.24 Register Name: config23– Address: 0x17, Default: 0x0000
        1. Table 29. Register Name: config23– Address: 0x17, Default: 0x0000
      25. 7.6.25 Register Name: config24– Address: 0x18, Default: 0x0000
        1. Table 30. Register Name: config24– Address: 0x18, Default: 0x0000
      26. 7.6.26 Register Name: config25– Address: 0x19, Default: 0x0000
        1. Table 31. Register Name: config25– Address: 0x19, Default: 0x0000
      27. 7.6.27 Register Name: config127– Address: 0x7F, Default: 0x0045
        1. Table 32. Register Name: config127– Address: 0x7F, Default: 0x0045
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 技术参数定义
    2. 11.2 相关链接
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.1 Register Name: config0 – Address: 0x00, Default: 0x4FC

Table 6. Register Name: config0 – Address: 0x00, Default: 0x4FC

Register Name Addr (Hex) Bit Name Function Default Value
config0 0x00 15 qmc_offset_ena Enable the offset function when asserted. 0
14 dual_ena Utilizes both DACs when asserted. 0
FUSE controlled
13:12 chipwidth Programmable bits for setting the input interface width.
00: all 14 bits are used
01: upper 12 bits are used
10: upper 10 bits are used
11: upper 10 bits are used		 00
11 rev Reverses the input bits. When using the 7bit interface, this reverse each 7-bit input, however when using the 14-bit interface, all 14-bits are reversed as one word. 0
10 twos When asserted, this bit tells the chip to presume 2’s complement data is arriving at the input. Otherwise offset binary is presumed. 1
9 sif4_ena When asserted the SIF interface becomes a 4 pin interface. This bit has a lower priority than the dieid_ena bit. 0
8 reserved reserved 0
7 fifo_ena When asserted, the FIFO is absorbing the difference between INPUT clock and DAC clock. If it is not asserted then the FIFO buffering is bypassed but the reversing of bits and handling of offset binary input is still available. NOTE: When the FIFO is bypassed, the DACCCLK and DATACLK must be aligned or there may be timing errors; not recommended for actual application use. 1
6 alarm_out_ena When asserted the pin alarm becomes an output instead of a tri-stated pin. 1
5 alarm_out_pol This bit changes the polarity of the ALARM signal. (0=negative logic, 1=positive logic) 1
4 alignrx_ena When asserted the ALIGN pin receiver is powered up. NOTE: It is recommended to clear this bit when ALIGNP/N are not used (dual bus mode, and SYNC ONLY and SIF_SYNC modes in single bus mode). 1
3 lvdssyncrx_ena When asserted the SYNC pin receiver is powered up. NOTE: It is recommended to clear this bit when SYNCP/N are not used (dual bus mode, and SIF_SYNC mode in single bus mode.) 1
2 lvdsdataclk_ena When asserted the DATACLK pin receiver is powered up. 1
1 reserved reserved 0
0 synconly_ena When asserted, the chip is put into the SYNC ONLY mode where the SYNC pin is used as the sync input for both the front and back of the FIFO. 0