ZHCSBF0D August 2013 – February 2018 DAC3151 , DAC3161 , DAC3171
PRODUCTION DATA.
| MIN | TYP(2) | MAX | UNIT | |||||
|---|---|---|---|---|---|---|---|---|
| ANALOG OUTPUT | ||||||||
| ts(DAC) | Output settling time to 0.1% | Transition:
Code 0x0000 to 0x3FFF |
11 | ns | ||||
| tPD | Output propagation delay | Does not include digital latency | 2 | ns | ||||
| tr(IOUT) | Output rise time 10% to 90% | 200 | ps | |||||
| tf(IOUT) | Output fall time 90% to 10% | 200 | ps | |||||
| SERIAL PORT TIMING | ||||||||
| ts(SENDB) | Setup time, SDENB to rising edge of SCLK | 20 | ns | |||||
| ts(SDIO) | Setup time, SDIO to rising edge of SCLK | 10 | ns | |||||
| th(SDIO) | Hold time, SDIO from rising edge of SCLK | 5 | ns | |||||
| t(SCLK) | Period of SCLK | 100 | ns | |||||
| t(SCLKH) | High time of SCLK | 40 | ns | |||||
| t(SCLKL) | Low time of SCLK | 40 | ns | |||||
| td(DATA) | Data output delay after falling edge of SCLK | 10 | ns | |||||
| TRESET | Minimum RESTB pulse width | 25 | ns | |||||
| LVDS INPUT TIMING | ||||||||
| ts(DATA) | Setup time(1) | D[x:0] valid to DATACLK rising for full word interface mode;
space DA[x:0] valid to DA_CLK rising or falling for 7-bit mode |
datadly | clkdly | ||||
| 0 | 0 | –20 | ps | |||||
| 0 | 1 | –120 | ps | |||||
| 0 | 2 | –220 | ps | |||||
| 0 | 3 | –310 | ps | |||||
| 0 | 4 | –390 | ps | |||||
| 0 | 5 | –480 | ps | |||||
| 0 | 6 | –560 | ps | |||||
| 0 | 7 | –630 | ps | |||||
| 1 | 0 | 70 | ps | |||||
| 2 | 0 | 150 | ps | |||||
| 3 | 0 | 230 | ps | |||||
| 4 | 0 | 330 | ps | |||||
| 5 | 0 | 430 | ps | |||||
| 6 | 0 | 530 | ps | |||||
| 7 | 0 | 620 | ps | |||||
| th(DATA) | Hold time(1) | D[x:0] valid to DATACLK rising for full word interface mode;
space DA[x:0] valid to DA_CLK rising or falling for 7-bit bus mode |
datadly | clkdly | ||||
| 0 | 0 | 310 | ps | |||||
| 0 | 1 | 390 | ps | |||||
| 0 | 2 | 480 | ps | |||||
| 0 | 3 | 560 | ps | |||||
| 0 | 4 | 650 | ps | |||||
| 0 | 5 | 740 | ps | |||||
| 0 | 6 | 850 | ps | |||||
| 0 | 7 | 930 | ps | |||||
| 1 | 0 | 200 | ps | |||||
| 2 | 0 | 100 | ps | |||||
| 3 | 0 | 20 | ps | |||||
| 4 | 0 | –60 | ps | |||||
| 5 | 0 | –140 | ps | |||||
| 6 | 0 | –220 | ps | |||||
| 7 | 0 | –290 | ps | |||||
Figure 1. DAC3151 Input Data Timing Diagram
Figure 2. DAC3161 Input Data Timing Diagram
Figure 3. DAC3171 Input Data Timing Diagram for 7-Bit Interface Mode
Figure 4. DAC3171 Input Data Timing for 14-Bit Interface Mode