ZHCSD87 January   2015 CSD97394Q4M

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Powering CSD97394Q4M And Gate Drivers
      2. 7.3.2 Undervoltage Lockout Protection (UVLO)
      3. 7.3.3 PWM Pin
      4. 7.3.4 SKIP# Pin
        1. 7.3.4.1 Zero Crossing (ZX) Operation
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Curves
    3. 8.3 System Example
      1. 8.3.1 Power Loss Curves
      2. 8.3.2 Safe Operating Curves (SOA)
      3. 8.3.3 Normalized Curves
        1. 8.3.3.1 Calculating Power Loss and SOA
          1. 8.3.3.1.1 Design Example
          2. 8.3.3.1.2 Calculating Power Loss
          3. 8.3.3.1.3 Calculating SOA Adjustments
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  10. 10器件和文档支持
    1. 10.1 商标
    2. 10.2 静电放电警告
    3. 10.3 术语表
  11. 11机械封装和可订购信息
    1. 11.1 机械制图
    2. 11.2 建议印刷电路板 (PCB) 焊盘图案
    3. 11.3 建议模板开口

封装选项

机械数据 (封装 | 引脚)
  • DPC|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The Power Stage CSD97394Q4M is a highly optimized design for synchronous buck applications using NexFET devices with a 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict the product performance in the actual application.

8.2 Typical Application

CSD97394Q4M application_diagram_CSD97394.gifFigure 3. Application Schematic

8.2.1 Application Curves

TJ = 125°C, unless stated otherwise
CSD97394Q4M D002_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 4. Power Loss vs Output Current
CSD97394Q4M D004_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 6. Safe Operating Area – PCB Horizontal Mount (1)
CSD97394Q4M D006_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 8. Typical Safe Operating Area (1)
CSD97394Q4M D008_SLPS542.gif
IOUT = 20 A VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 10. Normalized Power Loss vs Input Voltage
CSD97394Q4M D010_SLPS542.gif
VIN = 12 V VDD = 5 V IOUT = 20 A
ƒSW = 500 kHz VOUT = 1.8 V
Figure 12. Normalized Power Loss vs Output Inductance
CSD97394Q4M D012_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
IOUT = 20 A LOUT = 0.29 µH
Figure 14. Driver Current vs Temperature
CSD97394Q4M D003_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 5. Power Loss vs Temperature
CSD97394Q4M D005_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 7. Safe Operating Area – PCB Vertical Mount (1)
CSD97394Q4M D007_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
IOUT = 20 A LOUT = 0.29 µH
Figure 9. Normalized Power Loss vs Frequency
CSD97394Q4M D009_SLPS542.gif
VIN = 12 V VDD = 5 V IOUT = 20 A
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 11. Normalized Power Loss vs Output Voltage
CSD97394Q4M D011_SLPS542.gif
VIN = 12 V VDD = 5 V IOUT = 20 A
LOUT = 0.29 µH VOUT = 1.8 V
Figure 13. Driver Current vs Frequency
  1. The Typical CSD97394Q4M System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness. See the System Example section for detailed explanation.

8.3 System Example

8.3.1 Power Loss Curves

MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 4 plots the power loss of the CSD97394Q4M as a function of load current. This curve is measured by configuring and running the CSD97394Q4M as it would be in the final application (see Figure 15). The measured power loss is the CSD97394Q4M device power loss which consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Equation 1. Power Loss = (VINx IIN) + (VDD x IDD) – (VSW_AVG x IOUT)

The power loss curve in Figure 4 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.

8.3.2 Safe Operating Curves (SOA)

The SOA curves in the CSD97394Q4M datasheet give engineers guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 6 and Figure 8 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness.

8.3.3 Normalized Curves

The normalized curves in the CSD97394Q4M data sheet give engineers guidance on the Power Loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve.

CSD97394Q4M Power_Loss_Test_Circuit.gifFigure 15. Power Loss Test Circuit

8.3.3.1 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example). Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the following procedure will outline the steps engineers should take to predict product performance for any set of system conditions.

8.3.3.1.1 Design Example

Operating Conditions: Output Current (lOUT) = 10 A, Input Voltage (VIN ) = 7 V, Output Voltage (VOUT) = 1.5 V, Switching Frequency (ƒSW) = 800 kHz, Output Inductor (LOUT) = 0.2 µH

8.3.3.1.2 Calculating Power Loss

  • Typical Power Loss at 10 A = 2.1 W (Figure 4)
  • Normalized Power Loss for switching frequency ≈ 0.99 (Figure 9)
  • Normalized Power Loss for input voltage ≈ 1.10 (Figure 10)
  • Normalized Power Loss for output voltage ≈ 0.93 (Figure 11)
  • Normalized Power Loss for output inductor ≈ 1.10 (Figure 12)
  • Final calculated Power Loss = 2.1 W × 0.99 × 1.10 × 0.93 × 1.10 ≈ 2.3 W

8.3.3.1.3 Calculating SOA Adjustments

  • SOA adjustment for switching frequency ≈ –0.2°C (Figure 9)
  • SOA adjustment for input voltage ≈ 2.5°C (Figure 10)
  • SOA adjustment for output voltage ≈ 1.0°C (Figure 11)
  • SOA adjustment for output inductor ≈ 2.3°C (Figure 12)
  • Final calculated SOA adjustment = –0.2 + 2.5 + (–1.5) + 2.3 ≈ 3.1°C

CSD97394Q4M D013_SLPS542.gifFigure 16. Power Stage CSD97394Q4M SOA

In the design example above, the estimated power loss of the CSD97394Q4M would increase to 2.3 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 3.1°C. Figure 16 graphically shows how the SOA curve would be adjusted accordingly.

  1. Start by drawing a horizontal line from the application current to the SOA curve.
  2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
  3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 3.1°C. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature.