ZHCSD87 January   2015 CSD97394Q4M

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Powering CSD97394Q4M And Gate Drivers
      2. 7.3.2 Undervoltage Lockout Protection (UVLO)
      3. 7.3.3 PWM Pin
      4. 7.3.4 SKIP# Pin
        1. 7.3.4.1 Zero Crossing (ZX) Operation
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Curves
    3. 8.3 System Example
      1. 8.3.1 Power Loss Curves
      2. 8.3.2 Safe Operating Curves (SOA)
      3. 8.3.3 Normalized Curves
        1. 8.3.3.1 Calculating Power Loss and SOA
          1. 8.3.3.1.1 Design Example
          2. 8.3.3.1.2 Calculating Power Loss
          3. 8.3.3.1.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  10. 10器件和文档支持
    1. 10.1 商标
    2. 10.2 静电放电警告
    3. 10.3 术语表
  11. 11机械封装和可订购信息
    1. 11.1 机械制图
    2. 11.2 建议印刷电路板 (PCB) 焊盘图案
    3. 11.3 建议模板开口

封装选项

机械数据 (封装 | 引脚)
  • DPC|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

SON 3.5 × 4.5 mm
(Top View)
CSD97394Q4M PinOut_DPC-8_SLPS382_P2.gif

Pin Functions

PIN DESCRIPTION
NO. NAME
1 SKIP# This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the Sync FET. When SKIP# is High, the CSD95391Q4M operates in Forced Continuous Conduction Mode. A tri-state voltage on SKIP# puts the driver into a very low power state.
2 VDD Supply voltage to gate drivers and internal circuitry.
3 PGND Power ground, needs to be connected to Pin 9 and PCB
4 VSW Voltage switching node – pin connection to the output inductor.
5 VIN Input voltage pin. Connect input capacitors close to this pin.
6 BOOT_R Bootstrap capacitor connection. Connect a minimum 0.1 µF 16 V X5R, ceramic cap from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated. Boot_R is internally connected to VSW.
7 BOOT
8 PWM Pulse Width modulated tri-state input from external controller. Logic Low sets Control FET gate low and Sync FET gate high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if greater than the tri-state shutdown hold-off time (t3HT)
9 PGND Power ground