ZHCSCX3C April   2014  – November 2014 CSD95379Q3M

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Functional Description
        1. 7.2.1.1 Powering CSD95379Q3M and Gate Drivers
      2. 7.2.2 Undervoltage Lockout (UVLO) Protection
      3. 7.2.3 PWM Pin
      4. 7.2.4 SKIP# Pin
      5. 7.2.5 Zero Crossing (ZX) Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Loss Curves
      2. 8.1.2 Safe Operating Curves (SOA)
      3. 8.1.3 Normalized Curves
      4. 8.1.4 Calculating Power Loss and SOA
        1. 8.1.4.1 Design Example
        2. 8.1.4.2 Calculating Power Loss
        3. 8.1.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Electrical Performance
      2. 9.1.2 Thermal Performance
    2. 9.2 Layout Example
  10. 10器件和文档支持
    1. 10.1 商标
    2. 10.2 静电放电警告
    3. 10.3 术语表
  11. 11机械、封装和可订购信息
    1. 11.1 机械制图
    2. 11.2 建议印刷电路板 (PCB) 焊盘图案
    3. 11.3 建议模板开口

封装选项

机械数据 (封装 | 引脚)
  • DNS|10
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

Top View
CSD95379Q3M pinout_2.png

Pin Functions

PIN DESCRIPTION
NAME NUMBER
SKIP# 1 This pin enables the Diode Emulation function. When this pin is held low, Diode Emulation Mode is enabled for the sync FET. When SKIP# is high, the CSD95379Q3M operates in Forced Continuous Conduction Mode. A tri-state voltage on SKIP# puts the driver into a very-low power state.
VDD 3 Supply voltage to gate drivers and internal circuitry.
PGND 4 Power ground. Needs to be connected to pin 11 on the PCB.
VSW 5 Voltage switching node – pin connection to output inductor.
VIN 6 Input voltage pin. Connect input capacitors to close this pin.
BOOT_R 7 Bootstrap capacitor connection. Connect a minimum 0.1 µF 16 V X5R, ceramic capacitor from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.
BOOT 8
PWM 10 Pulse-width-modulated tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high sets control FET gate high and sync FET gate low. Open or High Z sets both MOSFET gates low if greater than the tri-state shutdown hold-off time (T3HT)
PGND 11 Power ground. Needs to be connected to pin 4 on the PCB.