ZHCSFS2 December   2016 CSD18543Q3A

PRODUCTION DATA.  

  1. 1特性
  2. 2应用范围
  3. 3说明
  4. 4修订历史记录
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6器件和文档支持
    1. 6.1 接收文档更新通知
    2. 6.2 社区资源
    3. 6.3 商标
    4. 6.4 静电放电警告
    5. 6.5 Glossary
  7. 7机械、封装和可订购信息
    1. 7.1 Q3A 封装尺寸
    2. 7.2 Q3A 建议的 PCB 布局
    3. 7.3 Q3A 建议的模板布局
    4. 7.4 Q3A 卷带信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DNH|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Specifications

5.1 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 60 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 48 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 1.5 2.0 2.7 V
RDS(on) Drain-to-source
on resistance		 VGS = 4.5 V, ID = 12 A 12.0 15.6 mΩ
VGS = 10 V, ID = 12 A 8.1 9.9 mΩ
gfs Transconductance VDS = 6 V, ID = 12 A 40 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 30 V, ƒ = 1 MHz 885 1150 pF
Coss Output capacitance 168 218 pF
Crss Reverse transfer capacitance 4.8 6.2 pF
RG Series gate resistance 0.5 1.0 Ω
Qg Gate charge total (4.5 V) VDS = 30 V, ID = 12 A 5.6 7.3 nC
Qg Gate charge total (10 V) 11.1 14.5
Qgd Gate charge gate-to-drain 1.7 nC
Qgs Gate charge gate-to-source 3.1 nC
Qg(th) Gate charge at Vth 2.0 nC
Qoss Output charge VDS = 30 V, VGS = 0 V 24 nC
td(on) Turnon delay time VDS = 30 V, VGS = 10 V,
IDS = 12 A, RG = 0 Ω		 9 ns
tr Rise time 18 ns
td(off) Turnoff delay time 8 ns
tf Fall time 4 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 12 A, VGS = 0 V 0.8 1.0 V
Qrr Reverse recovery charge VDS= 30 V, IF = 12 A,
di/dt = 300 A/μs		 37 nC
trr Reverse recovery time 27 ns

5.2 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 1.9 °C/W
RθJA Junction-to-ambient thermal resistance(1)(2) 55
(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
CSD18543Q3A m0161-01_lps202.gif
Max RθJA = 55°C/W when mounted on 1 in2 (6.45 cm2) of
2-oz (0.071-mm) thick Cu.
CSD18543Q3A m0161-02_lps202.gif
Max RθJA = 160°C/W when mounted on a minimum pad area of 2-oz (0.071-mm) thick Cu.

5.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise stated)
CSD18543Q3A D001_SLPS633.gif
Figure 1. Transient Thermal Impedance
CSD18543Q3A D002_SLPS633.gif
Figure 2. Saturation Characteristics
CSD18543Q3A D004_SLPS633.gif
ID = 12 A VDS = 30 V
Figure 4. Gate Charge
CSD18543Q3A D006_SLPS633.gif
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
CSD18543Q3A D008_SLPS633.gif
ID = 12 A
Figure 8. Normalized On-State Resistance vs Temperature
CSD18543Q3A D010_SLPS633.gif
Single pulse, max RθJC = 1.9°C/W
Figure 10. Maximum Safe Operating Area (SOA)
CSD18543Q3A D012_SLPS633.gif
Max RθJC = 1.9°C/W
Figure 12. Maximum Drain Current vs Temperature
CSD18543Q3A D003_SLPS633.gif
VDS = 5 V
Figure 3. Transfer Characteristics
CSD18543Q3A D005_SLPS633.gif
Figure 5. Capacitance
CSD18543Q3A D007_SLPS633.gif
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD18543Q3A D009_SLPS633.gif
Figure 9. Typical Diode Forward Voltage
CSD18543Q3A D011_SLPS633.gif
Figure 11. Single Pulse Unclamped Inductive Switching