ZHCSUO2E April 2004 – February 2024 CDCVF2509
PRODUCTION DATA
4.8 Typical Characteristics
Figure 4-1 Static Phase Error vs Load
Capacitance
Figure 4-3 Static Phase Error vs
Supply Voltage at FBOUT
Figure 4-5 Jitter vs Clock Frequency
at FBOUT
Figure 4-7 Supply Current vs Clock
Frequency
Figure 4-2 Static Phase Error vs Load
Capacitance
Figure 4-4 Static Phase Error vs
Clock Frequency
Figure 4-6 Analog Supply Current vs
Clock Frequency- Trace length FBOUT to FBIN = 5 mm, ZO = 50 Ω
- C(LY) = Lumped capacitive load Y1-n
- C(LFx) = Lumped feedback capacitance at FBOUT = FBIN
- C(LFx) = Lumped feedback capacitance at FBOUT = FBIN.