ZHCS887D May   2012  – April 2019 CDCUN1208LP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     引脚配置概述
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI), ERC(ADDR/CS), Mode
    6. 6.6  Universal Input (IN1, IN2) Characteristics
    7. 6.7  Clock Output Buffer Characteristics (Output Mode = LVDS)
    8. 6.8  Clock Output Buffer Characteristics (Output Mode = HCSL)
    9. 6.9  Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS)
    10. 6.10 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    11. 6.11 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Device Control Using Configuration Pins
        1. 8.3.1.1 Configuration of Output Type (OTTP)
        2. 8.3.1.2 Configuration of Edge Rate Control (ERC)
        3. 8.3.1.3 Control of Output Enable (OE)
      2. 8.3.2 Input Ports (IN1, IN2)
        1. 8.3.2.1 Configuration of the Input Type (ITTP)
        2. 8.3.2.2 Configuration of the IN2 Divider (INDIV)
      3. 8.3.3 Smart Input Multiplexer (INMUX)
        1. 8.3.3.1 Pin Configuration of the Smart Input Multiplexer (INMUX)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Control Using the Host Interface
        1. 8.4.1.1 OE and INSEL in Host Configuration Mode
    5. 8.5 Programming
      1. 8.5.1 Host Interface Hardware Information
        1. 8.5.1.1 SPI Communication
          1. 8.5.1.1.1 CDCUN1208LP SPI Addressing
          2. 8.5.1.1.2 Writing to the CDCUN1208LP
          3. 8.5.1.1.3 Reading From the CDCUN1208LP
          4. 8.5.1.1.4 Block Write/Read Operation
        2. 8.5.1.2 I2C Communication
          1. 8.5.1.2.1 Message Transmission
            1. 8.5.1.2.1.1 Data and Address Bits
            2. 8.5.1.2.1.2 Special Symbols – Start (S) and Stop (P)
            3. 8.5.1.2.1.3 Special Symbols – Acknowledge (ACK)
            4. 8.5.1.2.1.4 Generic Message Frame
            5. 8.5.1.2.1.5 CDCUN1208LP Message Format
            6. 8.5.1.2.1.6 CDCUN1208LP Device Addressing (I2C Address)
            7. 8.5.1.2.1.7 CDCUN1208LP Device Addressing (Register Address)
          2. 8.5.1.2.2 I2C Master and Slave Handshaking
          3. 8.5.1.2.3 Block Read/Write
          4. 8.5.1.2.4 I2C Timing
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers
        1. 8.6.1.1 Device Registers: Register 00-07
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 PCI Express Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
  10. 10Power Supply Recommendations
    1. 10.1 CDCUN1208LP Power Consumption
    2. 10.2 Device Power Supply Connections and Sequencing
    3. 10.3 Device Inputs (IN1, IN2)
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

RHB Package
VQFN 32-Pin
Top View
CDCUN1208LP po_cas928.gif

Pin Functions(1)

PIN TYPE DESCRIPTION
NAME NO.
GND Thermal Pad Power Power supply ground and thermal relief
DIVIDE 1 Input Input divider pin control
(HIGH = /4, LOW = /2, OPEN = /1)
INSEL 2 Input Input multiplexer control
IN1P 3 Input Universal input 1 – positive terminal
IN1N 4 Input Universal input 1 – negative terminal, ground if using IN1 in single-ended mode
VDD 5 Power Device power supply; provides power to the input section and clock distribution section. Use a power supply voltage that corresponds to the switching levels of clock inputs (such as 1.8 V, 2.5 V, or 3.3 V).
IN2P 6 Input Universal input 2 – positive terminal
IN2N 7 Input Universal input 2 – negative terminal, ground if using IN2 in single-ended mode
ITTP 8 Input Input type select (HIGH = HCSL, LOW = LVDS, OPEN = LVCMOS)
OUT1P 9 Output Output 1 – positive terminal
OUT1N 10 Output Output 1 – negative terminal
VDDO1 11 Power Output power supply – OUT1, OUT2
OUT2P 12 Output Output 2 – positive terminal
OUT2N 13 Output Output 2 – negative terminal
VDDO2 14 Power Output power supply – OUT3, OUT4; output bank OUT1 – OUT4 regulator power supply (apply power if any of OUT1 – OUT4 are needed)
OUT3P 15 Output Output 3 – positive terminal
OUT3N 16 Output Output 3 – negative terminal
OUT4P 17 Output Output 4 – positive terminal
OUT4N 18 Output Output 4 – negative terminal
OTTP 19 Output Output type select (HIGH = HCSL, LOW = LVDS, OPEN = LVCMOS)
OUT5P 20 Output Output 5 – positive terminal
OUT5N 21 Output Output 5 – negative terminal
VDDO3 22 Power Output power supply - OUT5, OUT6
OUT6P 23 Output Output 6 – positive terminal
OUT6N 24 Output Output 6 – negative terminal
OUT7P 25 Output Output 7 – positive terminal
OUT7N 26 Output Output 7 – negative terminal
VDDO4 27 Power Output power supply – OUT7, OUT8 output bank OUT5 – OUT8 regulator power supply (apply power if any of OUT5 – OUT8 are needed)
OUT8P 28 Output Output 8 – positive terminal
OUT8N 29 Output Output 8 – negative terminal
MODE 30 Input Device control mode select
OPEN = Device configured through pins (pin mode)
HIGH = Device configured through I2C
LOW = Device configured through SPI
Note: For information on control through the serial interface (I2C/ SPI), see Device Control Using the Host Interface section.
ERC 31 Input Output edge rate control
HIGH = Medium, LOW = Slow, OPEN = Fast
OE 32 Input Device output enable
HIGH = Enable, LOW = Disable
(1) This pin list applies to operation of the device in pin mode. In host mode, certain pins take on an alternate function, as outlined in Table 8.