ZHCS887D May   2012  – April 2019 CDCUN1208LP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     引脚配置概述
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI), ERC(ADDR/CS), Mode
    6. 6.6  Universal Input (IN1, IN2) Characteristics
    7. 6.7  Clock Output Buffer Characteristics (Output Mode = LVDS)
    8. 6.8  Clock Output Buffer Characteristics (Output Mode = HCSL)
    9. 6.9  Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS)
    10. 6.10 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    11. 6.11 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Device Control Using Configuration Pins
        1. 8.3.1.1 Configuration of Output Type (OTTP)
        2. 8.3.1.2 Configuration of Edge Rate Control (ERC)
        3. 8.3.1.3 Control of Output Enable (OE)
      2. 8.3.2 Input Ports (IN1, IN2)
        1. 8.3.2.1 Configuration of the Input Type (ITTP)
        2. 8.3.2.2 Configuration of the IN2 Divider (INDIV)
      3. 8.3.3 Smart Input Multiplexer (INMUX)
        1. 8.3.3.1 Pin Configuration of the Smart Input Multiplexer (INMUX)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Control Using the Host Interface
        1. 8.4.1.1 OE and INSEL in Host Configuration Mode
    5. 8.5 Programming
      1. 8.5.1 Host Interface Hardware Information
        1. 8.5.1.1 SPI Communication
          1. 8.5.1.1.1 CDCUN1208LP SPI Addressing
          2. 8.5.1.1.2 Writing to the CDCUN1208LP
          3. 8.5.1.1.3 Reading From the CDCUN1208LP
          4. 8.5.1.1.4 Block Write/Read Operation
        2. 8.5.1.2 I2C Communication
          1. 8.5.1.2.1 Message Transmission
            1. 8.5.1.2.1.1 Data and Address Bits
            2. 8.5.1.2.1.2 Special Symbols – Start (S) and Stop (P)
            3. 8.5.1.2.1.3 Special Symbols – Acknowledge (ACK)
            4. 8.5.1.2.1.4 Generic Message Frame
            5. 8.5.1.2.1.5 CDCUN1208LP Message Format
            6. 8.5.1.2.1.6 CDCUN1208LP Device Addressing (I2C Address)
            7. 8.5.1.2.1.7 CDCUN1208LP Device Addressing (Register Address)
          2. 8.5.1.2.2 I2C Master and Slave Handshaking
          3. 8.5.1.2.3 Block Read/Write
          4. 8.5.1.2.4 I2C Timing
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers
        1. 8.6.1.1 Device Registers: Register 00-07
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 PCI Express Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
  10. 10Power Supply Recommendations
    1. 10.1 CDCUN1208LP Power Consumption
    2. 10.2 Device Power Supply Connections and Sequencing
    3. 10.3 Device Inputs (IN1, IN2)
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.11 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)

Unless otherwise noted, VDDOx as shown in Table sections, TA = –40°C to 85°C. ERC = Fast. For test configurations, see Figure 21 and Figure 22.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
1.8-V MODE
fout Output frequency range 0.0008 250 MHz
VOH LVCMOS high-level output voltage VDDOx = 1.7 V, IOH = –0.1 mA (All ERC Settings) 1.6
VDDOx = 1.7 V, IOH = –1.5 mA (ERC = SLOW) 1.4 V
VDDOx = 1.7 V, IOH = –3 mA (ERC = MED)
VDDOx = 1.7 V, IOH = –4 mA (ERC = FAST)
VDDOx = 1.7 V, IOH = –3 mA (ERC = SLOW) 1.1 V
VDDOx = 1.7 V, IOH = –5 mA (ERC = MED)
VDDOx = 1.7 V, IOH = –8 mA (ERC = FAST)
VOL LVCMOS low-level output voltage VDDOx = 1.7 V, IOL = 0.1 mA (All ERC Settings) 0.1 V
VDDOx = 1.7 V, IOL = 2 mA (ERC = SLOW) 0.3 V
VDDOx = 1.7 V, IOL = 3 mA (ERC = MED)
VDDOx = 1.7 V, IOL = 4 mA (ERC = FAST)
VDDOx = 1.7 V, IOL = 3 mA (ERC = SLOW) 0.6 V
VDDOx = 1.7 V, IOL = 5 mA (ERC = MED)
VDDOx = 1.7 V, IOL = 8 mA (ERC = FAST)
IOH LVCMOS high-level output current VDDOx = 1.8 V, VO = 0.5 V; TA = 25°C –23 mA
VDDOx = 1.8 V, VO = 0.9 V; TA = 25°C –18
IOL LVCMOS low-level output current VDDOx = 1.8 V, VO = 1.4 V; TA = 25°C 27 mA
VDDOx = 1.8 V, VO = 0.9 V; TA = 25°C 23
tPLH, tPHL Propagation delay 6.8 ns
tSLEW-RATE Output rise/fall slew rate ERC = Slow, 20% to 80%, fout = 100 MHz, CL = 8 pF 0.5 V/ns
ERC = Medium 20% to 80%, fout = 100 MHz, CL = 8 pF 0.8
ERC = Fast, 20% to 80%, fout = 250 MHz, CL = 8 pF 2.7
tjitt-add Additive jitter fOUT = 100 MHz, 10k-20M integration bandwidth 350 fs
tsk(o) Output skew(2) 130 ps
odc Output duty cycle(1),(3) fOUT = 100 MHz; Pdiv = 1, ERC = MED, FAST 45% 55%
tOE Output enable to stable clock output Pin mode. fout = 100 MHz, device in active mode with outputs disabled, OE asserted 2 µs
tPD PD de-asserted to stable clock output Host mode, fout = 100 MHz, device in power down mode, PD de-asserted 10 µs
tPU Time from power applied to stable clock output(4) Pin mode, fout = 100 MHz, OE asserted, measured from time VDD is valid to stable output. 1 ms
(1) Assumes 50% duty cycle at the input.
(2) The tsk(o) specification is only valid for equal loading with identical edge rates and output supply voltages.
(3) odc depends on output rise and fall time (tR/tF).
(4) Parameter depends significantly on power supply design and supply voltage rise time.
CDCUN1208LP cross_pt_v_cas928.gifFigure 1. HCSL Crossing Point Voltage
CDCUN1208LP variation_cas928.gifFigure 2. HCSL Variation of VCROSS Over All Rising Clock Edges
CDCUN1208LP Ring_back_cas928.gifFigure 3. HCSL Ring Back Margin and Timing
CDCUN1208LP rise_fall_t_cas928.gifFigure 4. HCSL Rise Fall Time and Edge Speed
CDCUN1208LP match_rise_fall_cas928.gifFigure 5. HCSL Rise Fall Time Matching
CDCUN1208LP HCSL_duty_cycle_cas928.gifFigure 6. HCSL Duty Cycle