SCAS862G November   2008  – July 2016 CDCE62005

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
    6. 6.6 SPI Bus Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
      1. 8.2.1 Interface and Control Block
      2. 8.2.2 Input Block
      3. 8.2.3 Output Block
      4. 8.2.4 Clock Divider Module 0-4
      5. 8.2.5 Synthesizer Block
      6. 8.2.6 Computing The Output Frequency
    3. 8.3 Feature Description
      1. 8.3.1  Phase Noise Analysis
      2. 8.3.2  Output To Output Isolation
      3. 8.3.3  Device Control
      4. 8.3.4  External Control Pins
      5. 8.3.5  Input Block
        1. 8.3.5.1  Universal Input Buffers (UIB)
        2. 8.3.5.2  LVDS Fail Safe Mode
        3. 8.3.5.3  Smart Multiplexer Controls
        4. 8.3.5.4  Smart Multiplexer Auto Mode
        5. 8.3.5.5  Smart Multiplexer Dividers
        6. 8.3.5.6  Output Block
        7. 8.3.5.7  Output Multiplexer Control
        8. 8.3.5.8  Output Buffer Control
        9. 8.3.5.9  Output Buffer Control - LVCMOS Configurations
        10. 8.3.5.10 Output Dividers
        11. 8.3.5.11 Digital Phase Adjust
        12. 8.3.5.12 Phase Adjust Example
        13. 8.3.5.13 Valid Register Settings for Digital Phase Adjust Blocks
        14. 8.3.5.14 Output Synchronization
        15. 8.3.5.15 Auxiliary Output
        16. 8.3.5.16 Synthesizer Block
        17. 8.3.5.17 Input Divider
        18. 8.3.5.18 Feedback and Feedback Bypass Divider
          1. 8.3.5.18.1 VCO Select
          2. 8.3.5.18.2 Prescaler
          3. 8.3.5.18.3 Charge Pump Current Settings
          4. 8.3.5.18.4 Loop Filter
        19. 8.3.5.19 Internal Loop Filter Component Configuration
        20. 8.3.5.20 External Loop Filter Component Configuration
      6. 8.3.6  Digital Lock Detect
      7. 8.3.7  Crystal Input Interference
      8. 8.3.8  VCO Calibration
      9. 8.3.9  Startup Time Estimation
      10. 8.3.10 Analog Lock Detect
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fan-Out Buffer
      2. 8.4.2 Clock Generator
      3. 8.4.3 Jitter Cleaner - Mixed Mode
        1. 8.4.3.1 Clocking ADCs with the CDCE62005
        2. 8.4.3.2 CDCE62005 SERDES Startup Mode
    5. 8.5 Programming
      1. 8.5.1 Interface and Control Block
        1. 8.5.1.1 Serial Peripheral Interface (SPI)
        2. 8.5.1.2 CDCE62005 SPI Command Structure
        3. 8.5.1.3 SPI Interface Master
        4. 8.5.1.4 SPI Consecutive Read/Write Cycles to the CDCE62005
        5. 8.5.1.5 Writing to the CDCE62005
        6. 8.5.1.6 Reading from the CDCE62005
        7. 8.5.1.7 Writing to EEPROM
      2. 8.5.2 Device Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers: Register 0 Address 0x00
      2. 8.6.2 Device Registers: Register 1 Address 0x01
      3. 8.6.3 Device Registers: Register 2 Address 0x02
      4. 8.6.4 Device Registers: Register 3 Address 0x03
      5. 8.6.5 Device Registers: Register 4 Address 0x04
      6. 8.6.6 Device Registers: Register 5 Address 0x05
      7. 8.6.7 Device Registers: Register 6 Address 0x06
      8. 8.6.8 Device Registers: Register 7 Address 0x07
      9. 8.6.9 Device Registers: Register 8 Address 0x08
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Frequency Synthesizer
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Documentation Support
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

10 Power Supply Recommendations

The CDCE62005 is a high performance device. Therefore careful attention must be paid to device configuration and printed circuit board layout with respect to power consumption. Table 49 provides the power consumption for the individual blocks within the CDCE62005. To estimate total power consumption, calculate the sum of the products of the number of blocks used and the power dissipated of each corresponding block.

Table 49. CDCE62005 Power Consumption

INTERNAL BLOCK POWER AT 3.3V (typ.) POWER DISSIPATION/ BLOCK NUMBER OF BLOCKS
Input Circuit 250 mW 1
PLL and VCO Core 500 mW 1
Output Dividers Divider = 1 60 mW 5
Divider > 1 180 mW
LVPECL Output Buffer 75 mW(1) 5
LVDS Output Buffer 76 mW 5
LVCMOS Output Buffer Static 7 mW 10
Transient, CL = load, fOUT = MHz output frequency, V = output swing 3.3 × V × fOUT × (CL + 20 × 10-12) × 103 10
(1) An additional ~50 mW of power is dissipated externally at the termination resistors per LVPECL output pair.

This power estimate determines the degree of thermal management required for a specific design. Employing the thermally enhanced printed circuit board layout shown in Figure 53 ensures that the thermal performance curves shown in Figure 52 apply. Observing good thermal layout practices enables the thermal pad on the backside of the QFN-48 package to provide a good thermal path between the die contained within the package and the ambient air. This thermal pad also serves as the ground connection the device. Therefore, a low inductance connection to the ground plane is essential.

Figure 53 shows a layout optimized for good thermal performance and a good power supply connection as well. The 7×7 filled via pattern facilitates both considerations. Finally, the recommended layout achieves RθJA = 27.3°C/W in still air and 20.3°C/W in an environment with 100 LFM airflow if implemented on a JEDEC compliant thermal test board..

CDCE62005 temp_vs_device_total_power_scas862_v2.png Figure 52. CDCE62005 Die Temperature vs Total Device Power
CDCE62005 pcb_lay_cas862.gif Figure 53. CDCE62005 Recommended PCB Layout