ZHCSQA3F November   1997  – March 2022 CD54HC4094 , CD74HC4094 , CD74HCT4094

PRODUCTION DATA  

  1. 1 特性
  2. 2 说明
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PW|16
  • NS|16
  • N|16
  • D|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.6 Switching Characteristics

Input tr, tf = 6 ns. Unless otherwise specified, CL = 50pF Parameter Measurement Information
PARAMETER VCC (V) 25°C –40 to 85°C –55 to 125°C UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tpd Propagation delay time
CP to QS1		 2 150 190 225 ns
4.5 12(3) 30 38 45
6 26 33 38
tpd CP to QS2 2 135 170 205 ns
4.5 11(3) 27 34 41
6 23 29 35
tpd CP to Qn 2 195 245 295 ns
4.5 16(3) 39 49 59
6 33 42 50
tt STR to Qn 2 180 225 270 ns
4.5 36 45 54
6 31 38 46
tPZH, tPZL Output enable to Qn 2 175 220 265 ns
4.5 35 44 53
6 30 37 45
tPHZ, tPLZ Output disable to Qn 2 125 155 190 ns
4.5 25 31 38
6 21 26 32
tTLH, tTHL Output transition time 2 75 95 110 ns
4.5 15 19 22
6 13 16 19
tPHZ, tPLZ Output disabling time 5 10(3) ns
ƒMAX Maximum CP frequency 5 60(3) MHz
CIN Input capacitance 10 10 10 pF
CPD Power dissipation capacitance(1), (2) 5 90(3) pF
CO Tri-state output capacitance 15 15 15 pF
HCT TYPES
tPLH,
tPHL		 Propagation delay time
CP to QS1		 4.5 16(3) 39 ns
CP to QS2 4.5 15(3) 36 ns
CP to Qn 4.5 18(3) 43 ns
STR to Qn 4.5 39 ns
tPZH, tPZL Output enable to Qn 4.5 35 ns
tPHZ, tPLZ Output disable to Qn 4.5 35 ns
tTLH, tTHL Output transition time 4.5 15 ns
tPHZ, tPLZ Output disabling time 5 14(3) ns
ƒMAX Maximum CP frequency 5 60(3) MHz
CIN Input capacitance 10 10 10 pF
CPD Power dissipation capacitance(1), (2) 5 110(3) pF
CO Tri-state output capacitance 15 15 15 pF
(1) CPD is used to determine the dynamic power consumption, per register.
(2) PD = VCC2 ƒi (CPD + CL) where ƒi = Input frequency, CL = Output load capacitance, VCC = Supply voltage.
(3) Typical value tested at 5V, CL = 15pF