ZHCSPZ5D February   1998  – February 2022 CD54HC166 , CD54HCT166 , CD74HC166 , CD74HCT166

PRODUCTION DATA  

  1. 1 特性
  2. 2 说明
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (1)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • N|16
  • D|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3 Device Functional Modes

Table 7-1 Truth Table(1)
INPUTS INTERNAL
Q STATES		 OUTPUT
Q7
MASTER RESET PARALLEL ENABLE CLOCK ENABLE CLOCK SERIAL PARALLEL
D0 D7 Q0 Q1
L X X X X X L L L
H X L L X X Q00 Q10 Q0
H L L ­↑ X a...h a b h
H H L ­↑ H X H Q0n Q6n
H H L ­↑ L X L Q0n Q6n
H X H ­↑ X X Q00 Q10 Q70
(1) H = High Voltage Level,
L = Low Voltage Level,
X = Don’t Care,
↑ ­= Transition from Low to High Level,
a...h = The level of steady-state input at inputs D0 thru D7, respectively,
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established
Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ­↑ transition of the clock.