ZHCSPL0C 数据表 | 德州仪器 TI.com.cn

ZHCSPL0C February 1998 – December 2021 CD54HC273 , CD54HCT273 , CD74HC273 , CD74HCT273

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机械数据 (封装 | 引脚)

J|20

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5.6 Switching Characteristics

Input t_r, t_f = 6 ns (See Parameter Measurement Information)

PARAMETER		TEST CONDITIONS	V_CC(V)	25℃		–40℃ to 85℃	–55℃ to 125℃	UNIT
PARAMETER		TEST CONDITIONS	V_CC(V)	TYP	MAX	MAX	MAX	UNIT
HC TYPES
t_PLH, t_PHL	Propagation delay Clock to output	C_L = 50 pF	2		150	190	225	ns
			4.5		30	38	45
			6		26	30	38
		C_L = 15 pF	5	12
t_PHL	Propagation delay CLR to output	C_L = 50 pF	2		150	190	225	ns
			4.5		30	38	45
			6		26	30	38
t_TLH, t_THL	Output transition time	C_L = 50 pF	2		75	95	110	ns
			4.5		15	19	22
			6		13	16	19
C_IN	Input capacitance				10	10	10	pF
f_MAX	Maximum clock frequency	C_L = 15 pF	5	60				MHz
C_PD	Power dissipation capacitance⁽¹⁾⁽²⁾		5	25				pF
HCT TYPES
t_PLH, t_PHL	Propagation delay, Clock to output	C_L = 50 pF	4.5		30	38	45	ns
t_PLH, t_PHL	Propagation delay, Clock to output	C_L = 15 pF	5	12				ns
t_PHL	Propagation delay, CLR to output	C_L = 50 pF	4.5		32	40	48	ns
t_TLH, t_THL	Output transition time	C_L = 50 pF	4.5		15	19	22	ns
C_IN	Input capacitance				10	10	10	pF
f_MAX	Maximum clock frequency	C_L = 15 pF	5	50				MHz
C_PD	Power dissipation capacitance⁽¹⁾⁽²⁾		5	25				pF

(1) C_PD is used to determine the dynamic power consumption, per flip-flop.

(2) P_D = C_PD V_CC² f_i + Σ (C_L V_CC² + f_O) where f_i = input frequency, f_O = output frequency, C_L = output load capacitance, V_CC = supply voltage.