ZHCSEJ8B January   2011  – December 2015

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General Purpose I/O
    6. 7.6  Supply Current
    7. 7.7  REG27 LDO
    8. 7.8  Coulomb Counter
    9. 7.9  ADC
    10. 7.10 External Capacitor Voltage Balance Drive
    11. 7.11 Capacitor Voltage Monitor
    12. 7.12 Internal Temperature Sensor
    13. 7.13 Thermistor Measurement Support
    14. 7.14 Internal Thermal Shutdown
    15. 7.15 High-Frequency Oscillator
    16. 7.16 Low-Frequency Oscillator
    17. 7.17 RAM Backup
    18. 7.18 Flash
    19. 7.19 Current Protection Thresholds
    20. 7.20 Current Protection Timing
    21. 7.21 Timing Requirements: SMBus
    22. 7.22 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Super Capacitor Measurements
        1. 8.1.1.1 Voltage
        2. 8.1.1.2 Current, Charge and Discharge Counting
        3. 8.1.1.3 Device Calibration
        4. 8.1.1.4 Temperature
        5. 8.1.1.5 Series Capacitor Configuration
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Capacitance Monitoring and Learning
        1. 8.3.1.1 Monitoring and Control Operational Overview
        2. 8.3.1.2 Main Monitoring Registers
        3. 8.3.1.3 Initial Capacitance at Device Reset
        4. 8.3.1.4 Qualified Capacitance Learning
        5. 8.3.1.5 Health Determination
        6. 8.3.1.6 ESR Measurement
        7. 8.3.1.7 Monitor Operating Modes
      2. 8.3.2 Capacitor Voltage Balancing
      3. 8.3.3 Charge Control
        1. 8.3.3.1 Charge Termination
        2. 8.3.3.2 CHG Over Ride Control
      4. 8.3.4 Lifetime Data Gathering
        1. 8.3.4.1 Lifetime Maximum Temperature
        2. 8.3.4.2 Lifetime Minimum Temperature
        3. 8.3.4.3 Lifetime Maximum Capacitor Voltage
      5. 8.3.5 Safety Detection Features
        1. 8.3.5.1  Capacitor Overvoltage (OV)
        2. 8.3.5.2  Capacitor Voltage Imbalance (CIM)
        3. 8.3.5.3  Weak Capacitor (CLBAD)
        4. 8.3.5.4  Overtemperature (OT)
        5. 8.3.5.5  Overcurrent During Charging (OC Chg)
        6. 8.3.5.6  Overcurrent During Discharging (OC Dsg)
        7. 8.3.5.7  Short-Circuit During Charging (SC Chg)
        8. 8.3.5.8  Short-Circuit During Discharging (SC Dsg)
        9. 8.3.5.9  AFE Watchdog (WDF)
        10. 8.3.5.10 Integrated AFE Communication Fault (AFE_C)
        11. 8.3.5.11 Data Flash Fault (DFF)
        12. 8.3.5.12 FAULT Indication (FAULT Pin)
      6. 8.3.6 Communications
        1. 8.3.6.1 SMBus On and Off State
      7. 8.3.7 Security (Enables and Disables Features)
      8. 8.3.8 Measurement System Calibration
        1. 8.3.8.1  Coulomb Counter Deadband
        2. 8.3.8.2  Auto Calibration
        3. 8.3.8.3  Current Gain
        4. 8.3.8.4  CC Delta
        5. 8.3.8.5  Cap1 K-factor
        6. 8.3.8.6  Cap2 K-factor
        7. 8.3.8.7  Cap3 K-factor
        8. 8.3.8.8  Cap4 K-factor
        9. 8.3.8.9  Cap5 K-factor
        10. 8.3.8.10 K-factor Override Flag
        11. 8.3.8.11 System Voltage K-factor
        12. 8.3.8.12 Stack Voltage K-factor
        13. 8.3.8.13 K-factor Stack Override Flag
        14. 8.3.8.14 CC Offset
        15. 8.3.8.15 Board Offset
        16. 8.3.8.16 Int Temp Offset
        17. 8.3.8.17 Ext1 Temp Offset
        18. 8.3.8.18 CC Current
        19. 8.3.8.19 Voltage Signal
        20. 8.3.8.20 Temp Signal
        21. 8.3.8.21 CC Offset Time
        22. 8.3.8.22 ADC Offset Time
        23. 8.3.8.23 Current Gain Time
        24. 8.3.8.24 Voltage Time
        25. 8.3.8.25 Temperature Time
        26. 8.3.8.26 Cal Mode Timeout
        27. 8.3.8.27 Ext Coef a1..a5, b1..b4, Ext rc0, Ext adc0
        28. 8.3.8.28 Rpad
        29. 8.3.8.29 Rint
        30. 8.3.8.30 Int Coef 1..4, Int Min AD, Int Max Temp
        31. 8.3.8.31 Filter
        32. 8.3.8.32 Deadband
        33. 8.3.8.33 CC Deadband
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Power Modes
    5. 8.5 Programming
      1. 8.5.1 Communications
        1. 8.5.1.1 bq33100 Slave Address
        2. 8.5.1.2 SMBus On and Off State
        3. 8.5.1.3 Packet Error Checking
      2. 8.5.2 SBS Commands
        1. 8.5.2.1 SBS Command Summary
        2. 8.5.2.2 SBS Command Details
          1. 8.5.2.2.1  ManufacturerAccess (0x00)
            1. 8.5.2.2.1.1  Device Type (0x0001)
            2. 8.5.2.2.1.2  Firmware Version (0x0002)
            3. 8.5.2.2.1.3  Hardware Version (0x0003)
            4. 8.5.2.2.1.4  DF Checksum (0x0004)
            5. 8.5.2.2.1.5  Seal Device (0x0020)
            6. 8.5.2.2.1.6  Lifetime and Capacitor Balancing Enable (0x0021)
            7. 8.5.2.2.1.7  FAULT Activation (0x0030)
            8. 8.5.2.2.1.8  FAULT Clear (0x0031)
            9. 8.5.2.2.1.9  CHGLVL0 Activation (0x0032)
            10. 8.5.2.2.1.10 CHGLVL0 Clear (0x0033)
            11. 8.5.2.2.1.11 CHGLVL1 Activation (0x0033)
            12. 8.5.2.2.1.12 CHGLVL1 Clear (0x0034)
            13. 8.5.2.2.1.13 Learn Load Activation (0x0037)
            14. 8.5.2.2.1.14 Learn Load Clear (0x0038)
            15. 8.5.2.2.1.15 Calibration Mode (0x0040)
            16. 8.5.2.2.1.16 Reset (0x0041)
            17. 8.5.2.2.1.17 Unseal Device (UnsealKey)
            18. 8.5.2.2.1.18 Extended SBS Commands
          2. 8.5.2.2.2  Temperature (0x08)
          3. 8.5.2.2.3  Voltage (0x09)
          4. 8.5.2.2.4  Current (0x0a)
          5. 8.5.2.2.5  ESR (0x0b)
          6. 8.5.2.2.6  RelativeStateofCharge (0x0d)
          7. 8.5.2.2.7  Health (0x0e)
          8. 8.5.2.2.8  Capacitance (0x10)
          9. 8.5.2.2.9  ChargingCurrent (0x14)
          10. 8.5.2.2.10 ChargingVoltage (0x15)
          11. 8.5.2.2.11 CapacitorVoltage5..1 (0x3b..0x3f)
          12. 8.5.2.2.12 Extended SBS Commands
            1. 8.5.2.2.12.1 FETControl(0x46)
            2. 8.5.2.2.12.2 SafetyAlert (0x50)
            3. 8.5.2.2.12.3 SafetyStatus (0x51)
            4. 8.5.2.2.12.4 OperationStatus (0x54)
            5. 8.5.2.2.12.5 SystemVoltage (0x5a)
            6. 8.5.2.2.12.6 UnSealKey(0x60)
            7. 8.5.2.2.12.7 ManufacturerInfo(0x70)
      3. 8.5.3 Data Flash
        1. 8.5.3.1 Accessing Data Flash
        2. 8.5.3.2 Data Flash Interface
        3. 8.5.3.3 Data Flash Summary
        4. 8.5.3.4 Specific Data Flash Programming Details
          1. 8.5.3.4.1  OC Dsg
          2. 8.5.3.4.2  OC Dsg Time
          3. 8.5.3.4.3  SC Dsg Cfg
          4. 8.5.3.4.4  SC Chg Cfg
          5. 8.5.3.4.5  Initial Full Charge Capacitance
          6. 8.5.3.4.6  Full Charge Capacitance
          7. 8.5.3.4.7  Firmware Version
          8. 8.5.3.4.8  Hardware Revision
          9. 8.5.3.4.9  Manuf. Info
          10. 8.5.3.4.10 Operation Cfg
          11. 8.5.3.4.11 FET ACTION
          12. 8.5.3.4.12 FAULT
          13. 8.5.3.4.13 AFE State_CTL
          14. 8.5.3.4.14 Measurement Margin %
          15. 8.5.3.4.15 Timer
          16. 8.5.3.4.16 V Chg Nominal
          17. 8.5.3.4.17 V Chg A
          18. 8.5.3.4.18 V Chg B
          19. 8.5.3.4.19 V Chg Max
          20. 8.5.3.4.20 Min Voltage
          21. 8.5.3.4.21 Learning Frequency
          22. 8.5.3.4.22 Dsg Current Threshold
          23. 8.5.3.4.23 Chg Current Threshold
          24. 8.5.3.4.24 Quit Current
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting Number of Series Capacitor Support
        2. 9.2.2.2 Selecting Charging Voltage Values
        3. 9.2.2.3 Learning Frequency Selection
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VMAX Supply voltage VCC w.r.t. GND –0.3 34 V
VIN Input voltage VC1, VCC VVC2 – 0.3 VVC2 + 8.5 or 34, whichever is lower V
VC2 VVC3 – 0.3 VVC3 + 8.5 V
VC3 VVC4 – 0.3 VVC4 + 8.5 V
VC4 VSRP – 0.3 VSRP + 8.5 V
SRP, SRN –0.3 VREG27 V
SDA, SCL –0.3 6.0 V
CHGOR –0.3 VCC V
TS, VC5, CHGLVL0, CHGLVL1, FAULT –0.3 VREG27 + 0.3 V
VO Output voltage CHG –0.3 VCC V
VC5BAL –0.3 VREG27 + 0.3 V
RBI, REG27 –0.3 2.75 V
ISS Maximum combined sink current for input pins 50 mA
TFUNC Functional temperature –40 110 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage VCC 25 V
VCC 3.8 VVC2 + 5
VSTARTUP Start up voltage at VCC 5.2 5.5 V
VSHUTDOWN VCC or VCC, whichever is higher 3 3.2 3.3 V
VIN Input voltage VC1, VCC VVC2 VVC2 + 5 V
VC2 VVC3 VVC3 + 5
VC3 VVC4 VVC4 + 5
VC4 VSRP VSRP + 5
VCn – VC(n + 1), (n=1, 2, 3, 4 ) 0 5
VC5 0 1
VCC 25
CHGOR 0 VCC – 0.3 V
SRP to SRN –0.3 1 V
CREG27 External 2.7-V REG capacitor 1 μF
TOPR Operating temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) bq33100 UNIT
PW (TSSOP)
24 PINS
RθJA Junction-to-ambient thermal resistance 83.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 16.5 °C/W
RθJB Junction-to-board thermal resistance 39.4 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 38.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: General Purpose I/O

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage SDA, SCL, TS, VC5 2 V
VIL Low-level input voltage SDA, SCL, TS, VC5 0.8 V
VOH Output voltage high SDA, SCL, VC5BAL, CHGLVL0, CHGLVL1, LLEN, FAULT, IL = –0.5 mA VREG27 – 0.5 V
VOL Low-level output voltage SDA, SCL, VC5BAL, CHGLVL0, CHGLVL1, LLEN, FAULT, IL = 7 mA 0.4 V
CIN Input capacitance 5 pF
Ilkg Input leakage current SDA, SCL, TS, VC5, CHGLVL0, CHGLVL1, LLEN, FAULT
SDA and SCL pulldown disabled		 1 μA
VCHGOR CHG Over Ride active high 0.8 2 3.2 V
RPD(SMBx) SDA and SCL pulldown TA = –40°C to 100°C 600 950 1300 kΩ
RPAD Pad resistance TS 87 110 Ω

7.6 Supply Current

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Normal mode Firmware running, no flash writes 660 μA
ISHUTDOWN Shutdown mode TA = –40°C to 110°C 0.5 1 μA

7.7 REG27 LDO

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG– Regulator output voltage IREG27 = 10 mA TA = –40°C to 85°C 2.5 2.7 2.75 V
VREG27IT– Negative-going POR voltage At REG27 2.22 2.35 2.34 V
VREG27IT+ Positive-going POR voltage At REG27 2.25 2.5 2.6 V
ΔV(REGTEMP) Regulator output change with temperature IREG = 10 mA TA = –40°C to 85°C ±0.5%
ΔV(REGLINE) Line regulation IREG = 10 mA ±2 ±4 mV
ΔV(REGLOAD) Load regulation IREG = 0.2 to 10 mA ±20 ±40 mV
I(REGMAX) Current limit 25 50 mA

7.8 Coulomb Counter

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range –0.2 0.25 V
Conversion time Single conversion 250 ms
Effective resolution Single conversion 15 Bits
Integral nonlinearity TA = –25°C to 85°C ±0.007 ±0.034 %FSR
Offset error(1) TA = –25°C to 85°C 10 μV
Offset error drift 0.3 0.5 μV/°C
Full-scale error(2) –0.8% 0.2% 0.8%
Full-scale error drift 150 PPM/°C
Effective input resistance 2.5 MΩ
(1) Post Calibration Performance
(2) Uncalibrated performance. This gain error can be eliminated with external calibration.

7.9 ADC

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input voltage range TS, VC5 –0.2 0.8 × VREG27 V
Conversion time 31.5 ms
Resolution (no missing codes) 16 Bits
Effective resolution 14 15 Bits
Integral nonlinearity ±0.02 %FSR
Offset error(1) 70 160 μV
Offset error drift 1 μV/°C
Full-scale error VIN = 1 V –0.8% ±0.2% 0.4%
Full-scale error drift 150 PPM/°C
Effective input resistance 8 MΩ
(1) Channel to channel offset

7.10 External Capacitor Voltage Balance Drive

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RBAL_drive Internal pulldown resistance for external capacitor voltage balance Capacitor voltage balance ON for VC1,
VCi – VCi + 1 = 4 V, where i = 1 to approximately 4		 5.7 kΩ
Capacitor voltage balance ON for VC2,
VCi – VCi + 1 = 4 V, where = i = 1 to approximately 4		 3.7
Capacitor voltage balance ON for VC3,
VCi – VCi + 1 = 4 V, where = i = 1 to approximately 4		 1.75
Capacitor voltage balance ON for VC4,
VCi – VCi + 1 = 4 V, where = i = 1 to approximately 4		 0.85

7.11 Capacitor Voltage Monitor

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CAPACITOR Voltage Measurement Accuracy TA = –10°C to 60°C ±10 ±20 mV
TA = –40°C to 85°C ±10 ±35

7.12 Internal Temperature Sensor

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
T(TEMP) Temperature sensor accuracy ±3% °C

7.13 Thermistor Measurement Support

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RERR Internal resistor drift –230 ppm/°C
R Internal resistor TS 17 20 kΩ

7.14 Internal Thermal Shutdown

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
TMAX Maximum REG27 temperature 125 175 °C
TRECOVER Recovery hysteresis temperature 10 °C
(1) Parameters assured by design. Not production tested.

7.15 High-Frequency Oscillator

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(OSC) Operating frequency of CPU clock 2.097 MHz
f(EIO) Frequency error(1) TA = –20°C to 70°C –2% ±0.25% 2%
TA = –40°C to 85°C –3% ±0.25% 3%
t(SXO) Start-up time(2) TA = –25°C to 85°C 3 6 ms
(1) The frequency drift is included and measured from the trimmed frequency at VCC = VCC = 14.4 V, TA = 25°C
(2) The start-up time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered.

7.16 Low-Frequency Oscillator

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(LOSC) Operating frequency 32.768 MHz
f(LEIO) Frequency error(1) TA = –20°C to 70°C –1.5% ±0.25% 1.5%
TA = –40°C to 85°C –2.5% ±0.25% 2.5%
t(LSXO) Start-up time(2) TA = –25°C to 85°C 100 ms
(1) The frequency drift is included and measured from the trimmed frequency at VCC = VCC = 14.4 V, TA = 25°C.
(2) The start-up time is defined as the time it takes for the oscillator output frequency to be ±3%.

7.17 RAM Backup

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(RBI) RBI data-retention input current VRBI > V(RBI)MIN, VREG27 < VREG27IT-,
TA = 70°C to 110°C		 20 1500 nA
VRBI > V(RBI)MIN, VREG27 < VREG27IT-,
TA = –40°C to 70°C		 500
V(RBI) RBI data-retention voltage(1) 1 V
(1) Specified by design. Not production tested.

7.18 Flash

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Years
Flash programming write-cycles 20k Cycles
t(ROWPROG) Row programming time 2 ms
t(MASSERASE) Mass-erase time 250 ms
t(PAGEERASE) Page-erase time 25 ms
ICC(PROG) Flash-write supply current 4 6 mA
ICC(ERASE) Flash-erase supply current TA = –40°C to 0°C 8 22 mA
TA = 0°C to 85°C 3 15
(1) Specified by design. Not production tested

7.19 Current Protection Thresholds

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(OCD) OCD detection threshold voltage range, typical RSNS = 0 RSNS is set in STATE_CTL register 50 200 mV
RSNS = 1 25 100
ΔV(OCDT) OCD detection threshold voltage program step RSNS = 0 10 mV
RSNS = 1 5
V(SCCT) SCC detection threshold voltage range, typical RSNS = 0 –100 –300 mV
RSNS = 1 –50 –225
ΔV(SCCT) SCC detection threshold voltage program step RSNS = 0 –50 mV
RSNS = 1 –25
V(SCDT) SCD detection threshold voltage range, typical RSNS = 0 100 450 mV
RSNS = 1 50 225
ΔV(SCDT) SCD detection threshold voltage program step RSNS = 0 50 mV
RSNS = 1 25
V(OFFSET) SCD, SCC and OCD offset –10 10 mV
V(Scale_Err) SCD, SCC and OCD scale error –10% 10%

7.20 Current Protection Timing

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
MIN NOM MAX UNIT
t(OCDD) Overcurrent in discharge delay 1 31 ms
t(OCDD_STEP) OCDD step options 2 ms
t(SCDD) Short circuit in discharge delay AFE.STATE_CNTL[SCDDx2] = 0 0 915 μs
AFE.STATE_CNTL[SCDDx2] = 1 0 1830
t(SCDD_STEP) SCDD step options AFE.STATE_CNTL[SCDDx2] = 0 61 μs
AFE.STATE_CNTL[SCDDx2] = 1 122
t(SCCD) Short circuit in charge delay 0 915 μs
t(SCCD_STEP) SCCD step options 61 μs
t(DETECT) Current fault detect time VSRP-SRN = VTHRESH + 12.5 mV,
TA = –40°C to 85°C		 35 160 μs
tACC Overcurrent and short circuit delay time accuracy Accuracy of typical delay time with WDI active –20% 20%
Accuracy of typical delay time with no WDI input –50% 50%

7.21 Timing Requirements: SMBus

Typical values stated where TA = 25°C and VCC = VCC = 14.4 V, Minimum and maximum values stated where TA = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)
MIN NOM MAX UNIT
fSMB SMBus operating frequency Slave mode, SCL 50% duty cycle 10 100 kHz
fMAS SMBus master clock frequency Master mode, no clock low slave extend 51.2 kHz
tBUF Bus free time between start and stop 4.7 μs
tHD:STA Hold time after (repeated) start 4 μs
tSU:STA Repeated start setup time 4.7 μs
tSU:STO Stop setup time 4 μs
tHD:DAT Data hold time Receive mode 0 ns
Transmit mode 300
tSU:DAT Data setup time 250 ns
tTIMEOUT Error signal and detect See (1) 25 35 ms
tLOW Clock low period 4.7 μs
tHIGH Clock high period See (2) 4 50 μs
tLOW:SEXT Cumulative clock low slave extend time See (3) 25 ms
tLOW:MEXT Cumulative clock low master extend time See (4) 10 ms
tF Clock and data fall time See (5) 300 ns
tR Clock and data rise time See (6) 1000 ns
(1) The bq33100 times out when any clock low exceeds tTIMEOUT
(2) tHIGH maximum is the minimum bus idle time. SCL = SDA = 1 for t > 50 μs causes reset of any transaction involving bq33100 that is in progress.
(3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time tF = 0.9VDD to (VILMAX – 0.15)
bq33100 smbus_tim_1_lus928.gif Figure 1. SMBus Timing
bq33100 smbus_timout1_lus928.gif Figure 2. SMBus tTIMEOUT

7.22 Typical Characteristics

bq33100 C001_SLUS987.png Figure 3. Low Frequency Oscillator (LFO) Value Across Temperature With REG27 = 2.5 V
bq33100 C002_SLUS987.png Figure 4. REG27 Output Voltage Variation Across Temperature With a Nominal Load of 2 mA