ZHCSEV6A February   2016  – March 2016

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Digital Input and Output DC Characteristics
    7. 7.7  Power-On Reset
    8. 7.8  2.5-V LDO Regulator
    9. 7.9  Internal Clock Oscillators
    10. 7.10 ADC (Temperature and Cell Measurement) Characteristics
    11. 7.11 Integrating ADC (Coulomb Counter) Characteristics
    12. 7.12 Data Flash Memory Characteristics
    13. 7.13 I2C-Compatible Interface Communication Timing Characteristics
    14. 7.14 SDQ Switching Characteristics
    15. 7.15 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Data Commands
        1. 8.3.1.1 Standard Data Commands
          1. 8.3.1.1.1 Control(): 0x00/0x01
      2. 8.3.2 SDQ Signaling
      3. 8.3.3 Reset and Presence Pulse
      4. 8.3.4 WRITE
      5. 8.3.5 READ
      6. 8.3.6 Program Pulse
      7. 8.3.7 IDLE
      8. 8.3.8 CRC Generation
      9. 8.3.9 Communications
        1. 8.3.9.1 I2C Interface
        2. 8.3.9.2 I2C Time Out
        3. 8.3.9.3 I2C Command Waiting Time
        4. 8.3.9.4 I2C Clock Stretching
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 BAT Voltage Sense Input
        2. 9.2.2.2 SRP and SRN Current Sense Inputs
        3. 9.2.2.3 Sense Resistor Selection
        4. 9.2.2.4 TS Temperature Sense Input
        5. 9.2.2.5 Thermistor Selection
        6. 9.2.2.6 REGIN Power Supply Input Filtering
        7. 9.2.2.7 VCC LDO Output Filtering
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Sense Resistor Connections
      2. 11.1.2 Thermistor Connections
      3. 11.1.3 High-Current and Low-Current Path Separation
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档 
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Detailed Description

8.1 Overview

The bq27320 measures the voltage, temperature, and current to determine battery capacity and state of charge (SOC). The bq27320 monitors charge and discharge activity by sensing the voltage across a small-value resistor (5 mΩ to 20 mΩ typical) between the SRP and SRN pins and in series with the battery. By integrating charge passing through the battery, the battery’s SOC is adjusted during battery charge or discharge.

Measurements of OCV and charge integration determine chemical state of charge. The Qmax values are taken from a cell manufacturers' data sheet multiplied by the number of parallel cells. It is also used for the value in Design Capacity. It uses the OCV and Qmax value to determine StateOfCharge() on battery insertion, device reset, or on command. The FullChargeCapacity() is reported as the learned capacity available from full charge until Voltage() reaches the EDV0 threshold.

As Voltage() falls below the SysDown Set Volt Threshold, the Flags() [SYSDOWN] bit is set and SOC_INT will toggle once to provide a final warning to shut down the system. As Voltage() rises above SysDown Clear Voltage the [SYSDOWN] bit is cleared.

Additional details are found in the bq27320 Technical Reference Manual (SLUUBE6).

The fuel gauging is derived from the Compensated End of Discharge Voltage (CEDV) method, which uses a mathematical model to correlate remaining state of charge (RSOC) and voltage near to the end of discharge state. This requires a full discharge cycle for a single point FCC update. The implementation models cell voltage (OCV) as a function of battery state of charge (SOC), temperature, and current. The impedance is also a function of SOC and temperature, all of which can be satisfied by using seven parameters: EMF, C0, R0, T0, R1, TC, C1. For more detailed information, contact TI Applications Support at http://www-k.ext.ti.com/sc/technical-support/email-tech-support.asp?AAP.

8.2 Functional Block Diagram

bq27320 Func_Block.gif

8.3 Feature Description

The bq27320 accurately predicts the battery capacity and other operational characteristics of a single Li-based rechargeable cell. It can be interrogated by a system processor to provide cell information, such as time-to-empty (TTE) and state-of-charge (SOC) as well as SOC interrupt signal to the host.

Information is accessed through a series of commands, called Standard Commands. Further capabilities are provided by the additional Manufacturer Access Control subcommand set. Both sets of commands, indicated by the general format Command(), are used to read and write information contained within the device control and status registers, as well as its data flash locations. Commands are sent from system to gauge using the bq27320 device’s I2C serial communications engine, and can be executed during application development, system manufacture, or end-equipment operation.

Cell information is stored in the device in non-volatile flash memory. Many of these data flash locations are accessible during application development. They cannot, generally, be accessed directly during end-equipment operation. Access to these locations is achieved by either use of the bq27320 device’s companion evaluation software, through individual commands, or through a sequence of data-flash-access commands. To access a desired data flash location, the correct data flash address must be known.

The key to the bq27320 device’s high-accuracy gas gauging prediction is Texas Instruments CEDV algorithm. This algorithm uses cell measurements, characteristics, and properties to create state-of-charge predictions across a wide variety of operating conditions and over the lifetime of the battery.

The device measures charge and discharge activity by monitoring the voltage across a small-value series sense resistor (5 mΩ to 20 mΩ typical) located between the system’s VSS and the battery’s PACK– pin. When a cell is attached to the device, FCC is learned based on cell current and on cell voltage under-loading conditions when the EDV2 threshold is reached.

The device external temperature sensing is optimized with the use of a high accuracy negative temperature coefficient (NTC) thermistor with R25 = 10.0 kΩ ±1%. B25/85 = 3435K ± 1% (such as Semitec NTC 103AT). Alternatively, the bq27320 can also be configured to use its internal temperature sensor or receive temperature data from the host processor. When an external thermistor is used, a 18.2-kΩ pull-up resistor between BI/TOUT and TS pins is also required. The bq27320 uses temperature to monitor the battery-pack environment, which is used for fuel gauging and cell protection functionality.

To minimize power consumption, the device has different power modes: NORMAL, SNOOZE, SLEEP, HIBERNATE, and BAT INSERT CHECK. The bq27320 passes automatically between these modes, depending upon the occurrence of specific events, though a system processor can initiate some of these modes directly.

For complete operational details, refer to the bq27320 Technical Reference Manual (SLUUBE6).

NOTE

Formatting Conventions in this Document:

Commands: italics with parentheses() and no breaking spaces; for example, RemainingCapacity()

Data Flash: italics, bold, and breaking spaces; for example, Design Capacity

Register bits and flags: italics with brackets [ ]; for example, [TDA]

Data flash bits: italics, bold, and brackets [ ]; for example, [LED1]

Modes and states: ALL CAPITALS, for example; UNSEALED mode

8.3.1 Data Commands

8.3.1.1 Standard Data Commands

The bq27320 uses a series of 2-byte standard commands to enable system reading and writing of battery information. Each standard command has an associated command-code pair, as indicated in Table 1 (see the bq27320 Technical Reference Manual [SLUUBE6]). Because each command consists of two bytes of data, two consecutive I2C transmissions must be executed both to initiate the command function, and to read or write the corresponding two bytes of data.

Table 1. Standard Commands

NAME COMMAND CODE UNIT SEALED ACCESS
Control() / CONTROL_STATUS() CNTL 0x00 and 0x01 NA RW
AtRate() AR 0x02 and 0x03 mA RW
AtRateTimeToEmpty() ARTTE 0x04 and 0x05 Minutes R
Temperature() TEMP 0x06 and 0x07 0.1°K RW
Voltage() VOLT 0x08 and 0x09 mV R
BatteryStatus() Flags() 0x0A and 0x0B NA R
Current() Current() 0x0C and 0x0D mAh R
RemainingCapacity() RM 0x10 and 0x11 mAh R
FullChargeCapacity() FCC 0x12 and 0x13 mAh R
AverageCurrent() AI 0x14 and 0x15 mA R
TimeToEmpty() TTE 0x16 and 0x17 Minutes R
TimeToFull() TTF 0x18 and 0x19 Minutes R
StandbyCurrent() SI 0x1A and 0x1B mA R
StandbyTimeToEmpty() STTE 0x1C and 0x1D Minutes R
MaxLoadCurrent() MLI 0x1E and 0x1F mA R
MaxLoadTimeToEmpty() MLTTE 0x20 and 0x21 min R
AveragePower() AP 0x24 and 0x25 mW R
InternalTemperature() INTTEMP 0x28 and 0x29 0.1°K R
CycleCount() CC 0x2A and 0x2B num R
StateOfCharge() SOC 0x2C and 0x2D R
StateOfHealth() SOH 0x2E and 0x2F num R
ChargeVoltage() CV 0x30 and 0x31 mV R
ChargeCurrent() CC 0x32 and 0x33 mA R
BTPDischargeSet() 0x34 and 0x35 mAh R
BTPChargeSet() 0x36 and 0x37 mAh R
OperationStatus() 0x3A and 0x3B NA R
DesignCapacity() Design Cap 0x3C and 0x3D mAh R
ManufacturerAccessControl() MAC 0x3E and 0x3F
MACData() 0x40 through 0x5F
MACDataSum() 0x60
MACDataLen() 0x61
AnalogCount() 0x79
RawCurrent() 0x7A and 0x7B
RawVoltage() 0x7C and 0x7D
RawIntTemp() 0x7E and 0x7F
RawExtTemp() 0x80 and 0x81

8.3.1.1.1 Control(): 0x00/0x01

Issuing a Control() (Manufacturer Access Control or MAC) command requires a 2-byte subcommand. The subcommand specifies the particular MAC function desired. The Control() command allows the system to control specific features of the gas gauge during normal operation and additional features when the device is in different access modes, as described in the bq27320 Technical Reference Manual (SLUUBE6).

Table 2. Control() MAC Subcommands

CNTL / MAC FUNCTION SUBCOMMAND
CODE
SEALED
ACCESS?
DESCRIPTION
CONTROL_STATUS 0x0000 Yes Ignored by gauge (in previous devices would enable CONTROL_STATUS() read).
DEVICE_TYPE 0x0001 Yes Reports the device type (for example: 0x0320)
FW_VERSION 0x0002 Yes Reports the firmware version block (device, version, build, and so on)
HW_VERSION 0x0003 Yes Reports the hardware version of the device
IF_SUM 0x0004 Yes Reports Instruction flash checksum
STATIC_DF_SUM 0x0005 Yes Reports the static data flash checksum
CHEM_ID 0x0006 Yes Reports the chemical identifier of the CEDV configuration
PREV_MACWRITE 0x0007 Yes Returns previous Control() subcommand code
STATIC_CHEM_DF_SUM 0x0008 Yes Returns the chem ID checksum
BOARD_OFFSET 0x0009 Yes Invokes the board offset correction
CC_OFFSET 0x000A Yes Invokes the CC offset correction
CC_OFFSET_SAVE 0x000B Yes Saves the results of the offset calibration process
OCV_CMD 0x000C Yes Requests the gas gauge to take an OCV measurement
BAT_INSERT 0x000D Yes Forces BatteryStatus()[BATTPRES] bit set when Operation Config B [BIEnable] bit = 0
BAT_REMOVE 0x000E Yes Forces BatteryStatus()[BATTPRES] bit clear when Operation Config B [BIEnable] bit = 0
ALL_DF_SUM 0x0010 Yes Returns the checksum of the entire data flash except for calibration data
SET_HIBERNATE 0x0011 Yes Forces CONTROL_STATUS()[HIBERNATE] bit to 1
CLEAR_HIBERNATE 0x0012 Yes Forces CONTROL_STATUS()[HIBERNATE] bit to 0
SET_SNOOZE 0x0013 Yes Forces CONTROL_STATUS()[SNOOZE] bit to 1
CLEAR_SNOOZE 0x0014 Yes Forces CONTROL_STATUS()[SNOOZE] bit to 0
BATT_SELECT_0 0x0015 Yes Select Battery Profile 0
BATT_SELECT_1 0x0016 Yes Select Battery Profile 1
BATT_SELECT_2 0x0017 Yes Select Battery Profile 2
BATT_SELECT_3 0x0018 Yes Select Battery Profile 3
CAL_MODE 0x002D No Toggles OperationStatus()[CALMD]
SEALED 0x0030 No Places the gas gauge in SEALED access mode
SECURITY_KEYS 0x0035 No Read and Write Security Keys
RESET 0x0041 No Resets device
DEVICE_NAME 0x004a Yes Returns the device name
OPERATION_STATUS 0x0054 Yes This returns the same value as the OperationStatus() register.
GaugingStatus 0x0056 Yes Returns the information of CEDV gauge module status register
MANU_DATA 0x0070 Yes Returns the manufacturer info A block. This can be written directly when unsealed
GGSTATUS1 0x0073 Yes Returns internal gauge debug data block 1
GGSTATUS2 0x0074 Yes Returns internal gauge debug data block 2
GGSTATUS3 0x0075 Yes Returns internal gauge debug data block 3
GGSTATUS4 0x0076 Yes Returns internal gauge debug data block 4
EXIT_CAL 0x0080 No Instructs the fuel gauge to exit calibration mode
ENTER_CAL 0x0081 No Instructs the fuel gauge to enter calibration mode
RETURN_TO_ROM 0xF00 No Places the device in ROM mode
DF_ADDR_START 0x4000 No Direct DF read write access boundary
DF_ADDR_END 0x43FF No DF read write access boundary

8.3.2 SDQ Signaling

All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or to begin the start frame for a bit read. Figure 6 shows the initialization timing, whereas Figure 7 and Figure 8 show that the host initiates each bit by driving the DATA bus low for the start period, tWSTRB / tRSTRB. After the bit is initiated, either the host continues controlling the bus during a WRITE, or the bq27320 responds during a READ.

8.3.3 Reset and Presence Pulse

If the DATA bus is driven low for more than 120 μs, the bq27320 may be reset. Figure 6 shows that if the DATA bus is driven low for more than 480 μs, the bq27320 resets and indicates that it is ready by responding with a PRESENCE PULSE.

bq27320 reset_lus724.gif Figure 6. Reset Timing Diagram

8.3.4 WRITE

The WRITE bit timing diagram in Figure 7 shows that the host initiates the transmission by issuing the tWSTRB portion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for a WRITE 1.

bq27320 write_bit_lus526.gif Figure 7. Write Bit Timing Diagram

8.3.5 READ

The READ bit timing diagram in Figure 8 shows that the host initiates the transmission of the bit by issuing the tRSTRB portion of the bit. The bq27320 then responds by either driving the DATA bus low to transmit a READ 0 or releasing the DATA bus to transmit a READ 1.

bq27320 read_bit_lus526.gif Figure 8. Read Bit Timing Diagram

8.3.6 Program Pulse

bq27320 program_lus526.gif Figure 9. Program Pulse Timing Diagram

8.3.7 IDLE

If the bus is high, the bus is in the IDLE state. Bus transactions can be suspended by leaving the DATA bus in IDLE. Bus transactions can resume at any time from the IDLE state.

8.3.8 CRC Generation

The bq27320 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the bq27320 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 +1.

Under certain conditions, the bq27320 also generates an 8-bit CRC value using the same polynomial function shown and provides this value to the bus master to validate the transfer of command, address, and data bytes from the bus master to the bq27320. The bq27320 computes an 8-bit CRC for the command, address, and data bytes received for the WRITE MEMORY and the WRITE STATUS commands and then outputs this value to the bus master to confirm proper transfer. Similarly, the bq27320 computes an 8-bit CRC for the command and address bytes received from the bus master for the READ MEMORY, READ STATUS, and READ DATA/GENERATE 8-BIT CRC commands to confirm that these bytes have been received correctly. The CRC generator on the bq27320 is also used to provide verification of error-free data transfer as each page of data from the 1024-bit EPROM is sent to the bus master during a READ DATA/GENERATE 8-BIT CRC command, and for the eight bytes of information in the status memory field.

In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function previously given and compare the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the bq27320 (for ROM reads) or the 8-bit CRC value computed within the bq27320. The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. No circuitry on the bq27320 prevents a command sequence from proceeding if the CRC stored in or calculated by the bq27320 does not match the value generated by the bus master. Proper use of the CRC can result in a communication channel with a high level of integrity.

bq27320 udg_02065_lus526.gif Figure 10. 8-Bit CRC Generator Circuit (X8 + X5 + X4 + 1)

8.3.9 Communications

8.3.9.1 I2C Interface

The bq27320 supports the standard I2C read, incremental read, quick read, one-byte write, and incremental write functions. The 7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The first 8 bits of the I2C protocol are, therefore, 0xAA or 0xAB for write or read, respectively.

bq27320 i2c_packet_format.gif

The quick read returns data at the address indicated by the address pointer. The address pointer, a register internal to the I2C communication engine, increments whenever data is acknowledged by the bq27320 or the I2C master. “Quick writes” function in the same manner and are a convenient means of sending multiple bytes to consecutive command locations (such as two-byte commands that require two bytes of data).

The following command sequences are not supported:

Attempt to write a read-only address (NACK after data sent by master):

bq27320 i2c_invalid_write.gif

Attempt to read an address above 0x6B (NACK command):

bq27320 i2c_invalid_read.gif

8.3.9.2 I2C Time Out

The I2C engine releases both SDA and SCL if the I2C bus is held low for 2 seconds. If the bq27320 is holding the lines, releasing them frees them for the master to drive the lines. If an external condition is holding either of the lines low, the I2C engine enters the low-power sleep mode.

8.3.9.3 I2C Command Waiting Time

To ensure proper operation at 400 kHz, a t(BUF) ≥ 66 μs bus-free waiting time must be inserted between all packets addressed to the bq27320. In addition, if the SCL clock frequency (fSCL) is > 100 kHz, use individual 1-byte write commands for proper data flow control. The following diagram shows the standard waiting time required between issuing the control subcommand the reading the status result. For read-write standard command, a minimum of 2 seconds is required to get the result updated. For read-only standard commands, there is no waiting time required, but the host must not issue any standard command more than two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the watchdog timer.

bq27320 i2c_comm_wait.gif

8.3.9.4 I2C Clock Stretching

A clock stretch can occur during all modes of fuel gauge operation. In SNOOZE and HIBERNATE modes, a short clock stretch occurs on all I2C traffic as the device must wake-up to process the packet. In the other modes (BAT INSERT CHECK, NORMAL) clock stretching only occurs for packets addressed for the fuel gauge. The majority of clock stretch periods are small as the I2C interface performs normal data flow control. However, less frequent yet more significant clock stretch periods may occur as blocks of data flash are updated. The following table summarizes the approximate clock stretch duration for various fuel gauge operating conditions.

Gauging Mode Operating Condition/Comment Approximate
Duration
SLEEP HIBERNATE Clock stretch occurs at the beginning of all traffic as the device wakes up. ≤ 4 ms
BAT INSERT CHECK NORMAL Clock stretch occurs within the packet for flow control (after a start bit, ACK or first data bit). ≤ 4 ms
Data flash block writes. 72 ms
Restored data flash block write after loss of power. 116 ms

8.4 Device Functional Modes

To minimize power consumption, the device has different power modes: NORMAL, SNOOZE, SLEEP, HIBERNATE, and BAT INSERT CHECK. The bq27320 passes automatically between these modes, depending upon the occurrence of specific events, though a system processor can initiate some of these modes directly.

  • In NORMAL mode, the gas gauge is fully powered and can execute any allowable task.
  • In SNOOZE mode, low-frequency and high-frequency oscillators are active. Although the SNOOZE mode has higher current consumption than the SLEEP mode, it is also a reduced power mode.
  • In SLEEP mode, the gas gauge turns off the high-frequency oscillator and exists in a reduced-power state, periodically taking measurements and performing calculations.
  • In HIBERNATE mode, the gas gauge is in a low-power state, but can be woken up by communication or certain IO activity.
  • BAT INSERT CHECK mode is a powered up, but low-power halted, state, where the gas gauge resides when no battery is inserted into the system.