7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
|
MIN |
MAX |
UNIT |
VREGIN |
Regulator input range |
–0.3 |
5.5 |
V |
–0.3 |
6.0 (2) |
V |
VCE |
CE input pin |
–0.3 |
VREGIN + 0.3 |
V |
VCC |
Supply voltage range |
–0.3 |
2.75 |
V |
VIOD |
Open-drain I/O pins (SDA, SCL, SOC_INT) |
–0.3 |
5.5 |
V |
VBAT |
BAT input pin |
–0.3 |
5.5 |
V |
–0.3 |
6.0 (2) |
V |
VI |
Input voltage range to all other pins (BI/TOUT, TS, SRP, SRN, SDQ, BAT_GD) |
–0.3 |
VCC + 0.3 |
V |
TA |
Operating free-air temperature range |
–40 |
85 |
°C |
TFUNC |
Functional Temperature |
–40 |
110 |
°C |
TSTG |
Storage temperature range |
–65 |
150 |
°C |
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Condition not to exceed 100 hours at 25°C lifetime.
7.2 ESD Ratings
|
VALUE |
UNIT |
V(ESD) |
Electrostatic Discharge |
Human body model (HBM) ESD stress voltage(1), BAT pin |
1500 |
V |
Human-body model (HBM), all other pins |
2000 |
Charged-device model (CDM) ESD stress voltage(1) |
500 |
V |
(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
TA = -40°C to 85°C, VREGIN = VBAT = 3.6 V (unless otherwise noted)
|
MIN |
NOM |
MAX |
UNIT |
VREGIN |
Supply voltage |
No operating restrictions |
2.8 |
|
4.5 |
V |
No FLASH writes |
2.45 |
|
2.8 |
CREGIN |
External input capacitor for internal LDO between REGIN and VSS |
Nominal capacitor values specified. Recommend a 5% ceramic X5R type capacitor located close to the device. |
|
0.1 |
|
μF |
CLDO25 |
External output capacitor for internal LDO between VCC and VSS |
0.47 |
1 |
|
μF |
tPUCD |
Power-up communication delay |
|
|
250 |
|
ms |
7.4 Thermal Information
THERMAL METRIC(1) |
bq27320 |
UNIT |
YZF (DSBGA) |
15 PINS |
RθJA |
Junction-to-ambient thermal resistance |
70 |
°C/W |
RθJCtop |
Junction-to-case (top) thermal resistance |
17 |
°C/W |
RθJB |
Junction-to-board thermal resistance |
20 |
°C/W |
ψJT |
Junction-to-top characterization parameter |
1 |
°C/W |
ψJB |
Junction-to-board characterization parameter |
18 |
°C/W |
RθJCbot |
Junction-to-case (bottom) thermal resistance |
n/a |
°C/W |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,
SPRA953
7.5 Supply Current
TA = 25°C and VREGIN = VBAT = 3.6 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
ICC(1) |
Normal operating-mode current |
Fuel gauge in NORMAL mode ILOAD > Sleep Current |
|
118 |
|
μA |
ISNOOZE(1) |
Sleep+ operating mode current |
Fuel gauge in SNOOZE mode ILOAD < Sleep Current |
|
62 |
|
μA |
ISLP(1) |
Low-power storage-mode current |
Fuel gauge in SLEEP mode ILOAD < Sleep Current |
|
23 |
|
μA |
IHIB(1) |
Hibernate operating-mode current |
Fuel gauge in HIBERNATE mode ILOAD < Hibernate Current |
|
8 |
|
μA |
ISHD(1) |
SHUTDOWN mode current |
Fuel gauge in SHUTDOWN mode CE Pin < VIL(CE) max. |
|
1 |
|
μA |
(1) Specified by design. Not production tested.
7.6 Digital Input and Output DC Characteristics
TA = –40°C to 85°C, typical values at TA = 25°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VOL |
Output voltage, low (SCL, SDA, SOC_INT, SDQ, BAT_GD) |
IOL = 3 mA |
|
|
0.4 |
V |
VOH(PP) |
Output voltage, high (SDQ, BAT_GD) |
IOH = –1 mA |
VCC – 0.5 |
|
|
V |
VOH(OD) |
Output voltage, high (SDA, SCL, SOC_INT) |
External pullup resistor connected to VCC |
VCC – 0.5 |
|
|
VIL |
Input voltage, low (SDA, SCL) |
|
–0.3 |
|
0.6 |
V |
Input voltage, low (BI/TOUT) |
BAT INSERT CHECK mode active |
–0.3 |
|
0.6 |
VIH |
Input voltage, high (SDA, SCL) |
|
1.2 |
|
|
V |
Input voltage, high (BI/TOUT) |
BAT INSERT CHECK mode active |
1.2 |
|
VCC + 0.3 |
VIL(CE) |
Input voltage, low (CE) |
VREGIN = 2.8 to 4.5 V |
|
|
0.8 |
V |
VIH(CE) |
Input voltage, high (CE) |
2.65 |
|
|
Ilkg(1) |
Input leakage current (I/O pins) |
|
|
|
0.3 |
μA |
(1) Specified by design. Not production tested.
7.7 Power-On Reset
TA = –40°C to 85°C, typical values at TA = 25°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VIT+ |
Positive-going battery voltage input at VCC |
|
2.05 |
2.15 |
2.20 |
V |
VHYS |
Power-on reset hysteresis |
|
|
115 |
|
mV |
7.8 2.5-V LDO Regulator
TA = –40°C to 85°C, CLDO25 = 1μF, VREGIN = 3.6 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
NOM |
MAX |
UNIT |
VREG25 |
Regulator output voltage (VCC) |
2.8 V ≤ VREGIN ≤ 4.5V, IOUT ≤ 16 mA(1) |
2.3 |
2.5 |
2.6 |
V |
2.45 V ≤ VREGIN < 2.8V (low battery), IOUT ≤ 3 mA |
2.3 |
|
|
V |
(1) LDO output current, IOUT, is the total load current. LDO regulator should be used to power internal fuel gauge only.
7.9 Internal Clock Oscillators
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
fOSC |
High Frequency Oscillator |
|
|
8.389 |
|
MHz |
fLOSC |
Low Frequency Oscillator |
|
|
32.768 |
|
kHz |
7.10 ADC (Temperature and Cell Measurement) Characteristics
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VADC1 |
Input voltage range (TS) |
|
VSS – 0.125 |
|
2 |
V |
VADC2 |
Input voltage range (BAT) |
|
VSS – 0.125 |
|
5 |
V |
VIN(ADC) |
Input voltage range |
|
0.05 |
|
1 |
V |
GTEMP |
Internal temperature sensor voltage gain |
|
|
–2 |
|
mV/°C |
tADC_CONV |
Conversion time |
|
|
|
125 |
ms |
Resolution |
|
14 |
|
15 |
bits |
VOS(ADC) |
Input offset |
|
|
1 |
|
mV |
ZADC1(1) |
Effective input resistance (TS) |
|
8 |
|
|
MΩ |
ZADC2(1) |
Effective input resistance (BAT) |
bq27320 not measuring cell voltage |
8 |
|
|
MΩ |
bq27320 measuring cell voltage |
|
100 |
|
kΩ |
Ilkg(ADC)(1) |
Input leakage current |
|
|
|
0.3 |
μA |
(1) Specified by design. Not tested in production.
7.11 Integrating ADC (Coulomb Counter) Characteristics
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VSR |
Input voltage range, V(SRP) and V(SRN) |
VSR = V(SRP) – V(SRN) |
–0.125 |
|
0.125 |
V |
tSR_CONV |
Conversion time |
Single conversion |
|
1 |
|
s |
Resolution |
|
14 |
|
15 |
bits |
VOS(SR) |
Input offset |
|
|
10 |
|
μV |
INL |
Integral nonlinearity error |
|
|
±0.007% |
±0.034% |
FSR |
ZIN(SR)(1) |
Effective input resistance |
|
2.5 |
|
|
MΩ |
Ilkg(SR)(1) |
Input leakage current |
|
|
|
0.3 |
μA |
(1) Specified by design. Not tested in production.
7.12 Data Flash Memory Characteristics
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
tDR(1) |
Data retention |
|
10 |
|
|
Years |
Flash-programming write cycles(1) |
|
20,000 |
|
|
Cycles |
tWORDPROG(1) |
Word programming time |
|
|
|
2 |
ms |
ICCPROG(1) |
Flash-write supply current |
|
|
5 |
10 |
mA |
tDFERASE(1) |
Data flash master erase time |
|
200 |
|
|
ms |
tIFERASE(1) |
Instruction flash master erase time |
|
200 |
|
|
ms |
tPGERASE(1) |
Flash page erase time |
|
20 |
|
|
ms |
(1) Specified by design. Not production tested
7.13 I2C-Compatible Interface Communication Timing Characteristics
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
NOM |
MAX |
UNIT |
tr |
SCL/SDA rise time |
|
|
|
300 |
ns |
tf |
SCL/SDA fall time |
|
|
|
300 |
ns |
tw(H) |
SCL pulse duration (high) |
|
600 |
|
|
ns |
tw(L) |
SCL pulse duration (low) |
|
1.3 |
|
|
μs |
tsu(STA) |
Setup for repeated start |
|
600 |
|
|
ns |
td(STA) |
Start to first falling edge of SCL |
|
600 |
|
|
ns |
tsu(DAT) |
Data setup time |
|
100 |
|
|
ns |
th(DAT) |
Data hold time |
|
0 |
|
|
ns |
tsu(STOP) |
Setup time for stop |
|
600 |
|
|
ns |
t(BUF) |
Bus free time between stop and start |
|
66 |
|
|
μs |
fSCL |
Clock frequency(1) |
|
|
|
400 |
kHz |
(1) If the clock frequency (f
SCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (Refer to
I2C Interface and
I2C Command Waiting Time)
7.14 SDQ Switching Characteristics
TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
tc |
Bit cycle time(1) |
|
60 |
|
120 |
μs |
tWSTRB |
Write start cycle(1) |
|
1 |
|
15 |
μs |
tWDSU |
Write data setup(1) |
|
tWSTRB |
|
15 |
μs |
tWDH |
Write data hold(1) (2) |
|
60 |
|
tc |
μs |
trec |
Recovery time(1) |
|
1 |
|
|
μs |
For memory command only |
5 |
|
|
tRSTRB |
Read start cycle(1) |
|
1 |
|
13 |
μs |
tODD |
Output data delay(1) |
|
tRSTRB |
|
13 |
μs |
tODHO |
Output data hold(1) |
|
17 |
|
60 |
μs |
tRST |
Reset time(1) |
|
480 |
|
|
μs |
tPPD |
Presence pulse delay(1) |
|
15 |
|
60 |
μs |
tPP |
Presence pulse(1) |
|
60 |
|
240 |
μs |
tEPROG |
EPROM programming time |
|
2500 |
|
|
μs |
tPSU |
Program setup time |
|
5 |
|
|
μs |
tPREC |
Program recovery time |
|
5 |
|
|
μs |
tPRE |
Program rising-edge time |
|
|
|
5 |
μs |
tPFE |
Program falling-edge time |
|
|
|
5 |
μs |
tRSTREC |
|
|
480 |
|
|
μs |
(1) 5-kΩ series resistor between SDQ pin and VPU.
(2) tWDH must be less than tc to account for recovery.
Figure 1. I2C-Compatible Interface Timing Diagrams
7.15 Typical Characteristics
Figure 2. Regulator Output Voltage vs. Temperature
Figure 4. Low-Frequency Oscillator Frequency vs. Temperature
Figure 3. High-Frequency Oscillator Frequency vs. Temperature
Figure 5. Reported Internal Temperature Measurement vs. Temperature