SPRSP52A December   2019  – April 2020 AM6526 , AM6528 , AM6546 , AM6548

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC
        1. 4.3.1.1 MCU Domain
      2. 4.3.2  CAL
        1. 4.3.2.1 MAIN Domain
      3. 4.3.3  CPSW2G
        1. 4.3.3.1 MCU Domain
      4. 4.3.4  DDRSS
        1. 4.3.4.1 MAIN Domain
        2. 4.3.4.2 DDRSS Mapping
      5. 4.3.5  DMTIMER
        1. 4.3.5.1 MAIN Domain
        2. 4.3.5.2 MCU Domain
      6. 4.3.6  DSS
        1. 4.3.6.1 MAIN Domain
      7. 4.3.7  ECAP
        1. 4.3.7.1 MAIN Domain
      8. 4.3.8  EHRPWM
        1. 4.3.8.1 MAIN Domain
      9. 4.3.9  EQEP
        1. 4.3.9.1 MAIN Domain
      10. 4.3.10 GPIO
        1. 4.3.10.1 MAIN Domain
        2. 4.3.10.2 WKUP Domain
      11. 4.3.11 GPMC
        1. 4.3.11.1 MAIN Domain
      12. 4.3.12 HyperBus
        1. 4.3.12.1 MCU Domain
      13. 4.3.13 I2C
        1. 4.3.13.1 MAIN Domain
        2. 4.3.13.2 MCU Domain
        3. 4.3.13.3 WKUP Domain
      14. 4.3.14 MCAN
        1. 4.3.14.1 MCU Domain
      15. 4.3.15 MCASP
        1. 4.3.15.1 MAIN Domain
      16. 4.3.16 MCSPI
        1. 4.3.16.1 MAIN Domain
        2. 4.3.16.2 MCU Domain
      17. 4.3.17 MMCSD
        1. 4.3.17.1 MAIN Domain
      18. 4.3.18 CPTS
        1. 4.3.18.1 MAIN Domain
      19. 4.3.19 OLDI
        1. 4.3.19.1 MAIN Domain
      20. 4.3.20 OSPI
        1. 4.3.20.1 MCU Domain
      21. 4.3.21 PRU_ICSSG
        1. 4.3.21.1 MAIN Domain
      22. 4.3.22 SERDES
        1. 4.3.22.1 MAIN Domain
      23. 4.3.23 UART
        1. 4.3.23.1 MAIN Domain
        2. 4.3.23.2 MCU Domain
        3. 4.3.23.3 WKUP Domain
      24. 4.3.24 USB
        1. 4.3.24.1 MAIN Domain
      25. 4.3.25 Emulation and Debug
        1. 4.3.25.1 MAIN Domain
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Boot Mode Configuration
          1. 4.3.26.1.1 MAIN Domain
          2. 4.3.26.1.2 MCU Domain
        2. 4.3.26.2 Clock
          1. 4.3.26.2.1 MAIN Domain
          2. 4.3.26.2.2 WKUP Domain
        3. 4.3.26.3 System
          1. 4.3.26.3.1 MAIN Domain
          2. 4.3.26.3.2 WKUP Domain
        4. 4.3.26.4 Miscellaneous
          1. 4.3.26.4.1 WKUP Domain
        5. 4.3.26.5 EFUSE
          1. 4.3.26.5.1 MAIN Domain
          2. 4.3.26.5.2 MCU Domain
      27. 4.3.27 Power Supply
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 Voltage and Core Clock Specifications
    6. 5.6 Electrical Characteristics
      1. Table 5-5  I2C OPEN DRAIN DC Electrical Characteristics
      2. Table 5-6  Analog OSC Buffers DC Electrical Characteristics
      3. Table 5-7  Analog ADC DC Electrical Characteristics
      4. Table 5-8  DPHY CSI2 Buffers DC Electrical Characteristics
      5. Table 5-9  OLDI LVDS Buffers DC Electrical Characteristics
      6. Table 5-10 LVCMOS Buffers DC Electrical Characteristics
      7. Table 5-11 LVCMOS Buffers (Reset) DC Electrical Characteristics
      8. Table 5-12 LVCMOS-FS Buffers DC Electrical Characteristics
      9. 5.6.1      USBHS Buffers DC Electrical Characteristics
      10. 5.6.2      SERDES Buffers DC Electrical Characteristics
    7. 5.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-13 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.7.1      Hardware Requirements
      3. 5.7.2      Programming Sequence
      4. 5.7.3      Impact to Your Hardware Warranty
    8. 5.8 Thermal Resistance Characteristics
      1. Table 5-14 Thermal Resistance Characteristics
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
      2. 5.9.2 Power Supply Sequencing
        1. 5.9.2.1 Power Supply Slew Rate Requirement
        2. 5.9.2.2 VDDA_1P8_SERDES0 Supply Slew Rate Requirement
        3. 5.9.2.3 Power-Up Sequencing
        4. 5.9.2.4 Power-Down Sequencing
      3. 5.9.3 Reset Timing
        1. 5.9.3.1 Reset Electrical Data/Timing
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
          2. 5.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 5.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
          4. 5.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 5.9.4.1.5 Auxiliary OSC1 Not Used
          6. 5.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 5.9.4.1.7 WKUP_LFOSC0 LVCMOS Digital Clock Source
          8. 5.9.4.1.8 WKUP_LFOSC0 Not Used
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 PLLs
        4. 5.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 5.9.4.5 Module and Peripheral Clock Frequencies
      5. 5.9.5 Peripherals
        1. 5.9.5.1  VIN
        2. 5.9.5.2  CPSW2G
          1. 5.9.5.2.1 CPSW2G MDIO Interface Timings
          2. 5.9.5.2.2 CPSW2G RMII Timings
            1. Table 5-33 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-34 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-35 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          3. 5.9.5.2.3 CPSW2G RGMII Timings
            1. Table 5-36 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-37 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-38 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-39 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL - RGMII Mode
        3. 5.9.5.3  CSI2
        4. 5.9.5.4  DDRSS
        5. 5.9.5.5  DSS
        6. 5.9.5.6  eCAP
          1. Table 5-43 Timing Requirements for eCAP
          2. Table 5-44 Switching Characteristics for eCAP
        7. 5.9.5.7  eHRPWM
          1. Table 5-45 Timing Requirements for eHRPWM
          2. Table 5-46 Switching Characteristics for eHRPWM
        8. 5.9.5.8  eQEP
          1. Table 5-47 Timing Requirements for eQEP
          2. Table 5-48 Switching Characteristics for eQEP
        9. 5.9.5.9  GPIO
          1. Table 5-49 GPIO Timing Requirements
          2. Table 5-50 GPIO Switching Characteristics
        10. 5.9.5.10 GPMC
          1. 5.9.5.10.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-51 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            2. Table 5-52 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.9.5.10.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-53 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            2. Table 5-54 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.9.5.10.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-55 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            2. Table 5-56 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        11. 5.9.5.11 HyperBus
          1. Table 5-57 Timing Requirements for HyperBus Initialization
          2. Table 5-58 HyperBus 166 MHz Switching Characteristics
          3. Table 5-59 HyperBus 100 MHz Switching Characteristics
        12. 5.9.5.12 I2C
          1. Table 5-60 Timing Requirements for I2C Input Timings
          2. Table 5-61 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        13. 5.9.5.13 MCAN
        14. 5.9.5.14 MCASP
          1. Table 5-63 Timing Requirements for MCASP
        15. 5.9.5.15 MCSPI
          1. 5.9.5.15.1 SPI—Master Mode
            1. Table 5-65 Timing Requirements for SPI - Master Mode
          2. 5.9.5.15.2 MCSPI—Slave Mode
            1. Table 5-66 Timing Requirements for SPI - Slave Mode
        16. 5.9.5.16 eMMC/SD/SDIO
          1. 5.9.5.16.1 MMCi — eMMC/SD/SDIO Card Interface
            1. 5.9.5.16.1.1 Default speed Mode
            2. 5.9.5.16.1.2 High speed Mode
            3. 5.9.5.16.1.3 UHS-I SDR12 Mode
            4. 5.9.5.16.1.4 UHS-I SDR25 Mode
            5. 5.9.5.16.1.5 UHS-I SDR50 Mode
            6. 5.9.5.16.1.6 UHS-I SDR104 / HS200 Mode
            7. 5.9.5.16.1.7 UHS-I DDR50 Mode
        17. 5.9.5.17 NAVSS
          1. Table 5-80 Timing Requirements for CPTS Input
          2. Table 5-81 Switching Characteristics for CPTS Output
        18. 5.9.5.18 OSPI
          1. 5.9.5.18.1 OSPI with Data Training
            1. Table 5-82 OSPI Switching Characteristics - Data Training
          2. 5.9.5.18.2 OSPI without Data Training
            1. Table 5-83 OSPI Switching Characteristics - DDR Mode
            2. Table 5-84 OSPI Switching Characteristics - SDR Mode
            3. Table 5-85 OSPI Timing Requirements - DDR Mode
            4. Table 5-86 OSPI Timing Requirements - SDR Mode
        19. 5.9.5.19 OLDI
          1. Table 5-88 OLDI Switching Characteristics
        20. 5.9.5.20 PCIE
        21. 5.9.5.21 PRU_ICSSG
          1. 5.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)
            1. 5.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-89 PRU_ICSSG PRU Switching Characteristics - Direct Output Mode
            2. 5.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-90 PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode
            3. 5.9.5.21.1.3 PRU_ICSSG PRU Shift Mode Electrical Data and Timing
              1. Table 5-91 PRU_ICSSG PRU Timing Requirements - Shift In Mode
              2. Table 5-92 PRU_ICSSG PRU Switching Characteristics - Shift Out Mode
            4. 5.9.5.21.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing
              1. Table 5-93 PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-94 PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode
              3. Table 5-95 PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode
          2. 5.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 5.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing
              1. Table 5-96 PRU_ICSSG PWM Switching Characteristics
          3. 5.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
            1. 5.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing
              1. Table 5-97 PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx
              2. Table 5-98 PRU_ICSSG IEP Timing Requirements - Digital IOs
              3. Table 5-99 PRU_ICSSG IEP Timing Requirements - LATCHx_IN
          4. 5.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. 5.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing
              1. Table 5-100 PRU_ICSSG UART Timing Requirements
              2. Table 5-101 PRU_ICSSG UART Switching Characteristics
          5. 5.9.5.21.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)
            1. 5.9.5.21.5.1 PRU_ICSSG ECAP Electrical Data and Timing
              1. Table 5-102 PRU_ICSSG ECAP Timing Requirements
              2. Table 5-103 PRU_ICSSG ECAP Switching Characteristics
          6. 5.9.5.21.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 5.9.5.21.6.1 PRU_ICSSG MDIO Electrical Data and Timing
              1. Table 5-104 PRU_ICSSG MDIO Timing Requirements – MDIO_DATA
              2. Table 5-105 PRU_ICSSG MDIO Switching Characteristics – MDIO_CLK
              3. Table 5-106 PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA
            2. 5.9.5.21.6.2 PRU_ICSSG RGMII Electrical Data and Timing
              1. Table 5-107 PRU_ICSSG RGMII Timing Requirements - RGMII_RCLK
              2. Table 5-108 PRU_ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RCTL
              3. Table 5-109 PRU_ICSSG RGMII Switching Characteristics - RGMII_TCLK
              4. Table 5-110 PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TX_CTL
            3. 5.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing
              1. Table 5-111 PRU_ICSSG MII_RT Timing Requirements – MII_RXCLK
              2. Table 5-112 PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK
              3. Table 5-113 PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-114 PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
        22. 5.9.5.22 Timers
          1. Table 5-115 Timing Requirements for Timers
          2. Table 5-116 Switching Characteristics for Timers
        23. 5.9.5.23 UART
          1. Table 5-117 Timing Requirements for UART
          2. Table 5-118 Switching Characteristics Over Recommended Operating Conditions for UART
        24. 5.9.5.24 USB
      6. 5.9.6 Emulation and Debug
        1. 5.9.6.1 Debug Trace
        2. 5.9.6.2 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.9.6.2.1 JTAG Electrical Data and Timing
            1. Table 5-120 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-121 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 Arm Cortex-A53
      2. 6.2.2 Arm Cortex-R5F
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 PRU_ICSSG
        1. 6.3.1.1 PRU_ICSSG PRU and RTU_PRU Cores
        2. 6.3.1.2 PRU_ICSSG Broadside Accelerators Overview
        3. 6.3.1.3 PRU_ICSSG UART Module
        4. 6.3.1.4 PRU_ICSSG ECAP Module
        5. 6.3.1.5 PRU_ICSSG PWM Module
        6. 6.3.1.6 PRU_ICSSG MII_G_RT Module
        7. 6.3.1.7 PRU_ICSSG MII MDIO Module
        8. 6.3.1.8 PRU_ICSSG IEP
      2. 6.3.2 GPU
    4. 6.4 Other Subsystems
      1. 6.4.1 DMSC
      2. 6.4.2 MSMC
      3. 6.4.3 NAVSS
        1. 6.4.3.1 NAVSS0
        2. 6.4.3.2 MCU_NAVSS0
      4. 6.4.4 PDMA Controller
      5. 6.4.5 Peripherals
        1. 6.4.5.1  ADC
        2. 6.4.5.2  CAL
        3. 6.4.5.3  CPSW2G
        4. 6.4.5.4  DCC
        5. 6.4.5.5  DDRSS
        6. 6.4.5.6  DSS
        7. 6.4.5.7  ЕCAP
        8. 6.4.5.8  EPWM
        9. 6.4.5.9  ELM
        10. 6.4.5.10 ESM
        11. 6.4.5.11 EQEP
        12. 6.4.5.12 GPIO
        13. 6.4.5.13 GPMC
        14. 6.4.5.14 HyperBus
        15. 6.4.5.15 I2C
        16. 6.4.5.16 MCAN
        17. 6.4.5.17 MCASP
        18. 6.4.5.18 MCRC
        19. 6.4.5.19 MCSPI
        20. 6.4.5.20 MMCSD
        21. 6.4.5.21 OSPI
        22. 6.4.5.22 PCIE
        23. 6.4.5.23 SerDes
        24. 6.4.5.24 RTI
        25. 6.4.5.25 Timers
        26. 6.4.5.26 UART
        27. 6.4.5.27 USB
    5. 6.5 Identification
      1. 6.5.1 Revision Identification
      2. 6.5.2 Die Identification
      3. 6.5.3 JTAG Identification
      4. 6.5.4 ROM Code Identification
    6. 6.6 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 7.1.1.1 Power Distribution Network Implementation Guidance
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG and EMU
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 Hardware Design Guide for AM65x/DRA80xM Devices
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 DDR Board Design and Layout Guidelines
      2. 7.2.2 OSPI Board Design and Layout Guidelines
        1. 7.2.2.1 No Loopback & Internal Pad Loopback
        2. 7.2.2.2 External Board Loopback
        3. 7.2.2.3 DQS (only available in Octal Flash devices)
      3. 7.2.3 USB Design Guidelines
      4. 7.2.4 High Speed Differential Signal Routing Guidance
      5. 7.2.5 System Power Supply Monitor Design Guidelines
      6. 7.2.6 MMC Design Guidelines
      7. 7.2.7 Integrated Power Management Features
      8. 7.2.8 External Capacitors
        1. 7.2.8.1 LVCMOS External Capacitor Connections
      9. 7.2.9 Thermal Solution Guidance
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ACD|784
散热焊盘机械数据 (封装 | 引脚)
订购信息

MAIN Domain

Table 4-24 GPIO0 Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4]
GPIO0_0 General Purpose Input/Output IO M27
GPIO0_1 General Purpose Input/Output IO M23
GPIO0_2 General Purpose Input/Output IO M28
GPIO0_3 General Purpose Input/Output IO M24
GPIO0_4 General Purpose Input/Output IO N24
GPIO0_5 General Purpose Input/Output IO N27
GPIO0_6 General Purpose Input/Output IO N28
GPIO0_7 General Purpose Input/Output IO M25
GPIO0_8 General Purpose Input/Output IO N23
GPIO0_9 General Purpose Input/Output IO M26
GPIO0_10 General Purpose Input/Output IO P28
GPIO0_11 General Purpose Input/Output IO P27
GPIO0_12 General Purpose Input/Output IO N26
GPIO0_13 General Purpose Input/Output IO N25
GPIO0_14 General Purpose Input/Output IO P24
GPIO0_15 General Purpose Input/Output IO R27
GPIO0_16 General Purpose Input/Output IO R28
GPIO0_17 General Purpose Input/Output IO P25
GPIO0_18 General Purpose Input/Output IO P26
GPIO0_19 General Purpose Input/Output IO U28
GPIO0_20 General Purpose Input/Output IO T28
GPIO0_21 General Purpose Input/Output IO P23
GPIO0_22 General Purpose Input/Output IO R26
GPIO0_23 General Purpose Input/Output IO R23
GPIO0_24 General Purpose Input/Output IO T25
GPIO0_25 General Purpose Input/Output IO T24
GPIO0_26 General Purpose Input/Output IO R24
GPIO0_27 General Purpose Input/Output IO T23
GPIO0_28 General Purpose Input/Output IO R25
GPIO0_29 General Purpose Input/Output IO T27
GPIO0_30 General Purpose Input/Output IO AF18
GPIO0_31 General Purpose Input/Output IO AE18
GPIO0_32 General Purpose Input/Output IO AH17
GPIO0_33 General Purpose Input/Output IO AG18
GPIO0_34 General Purpose Input/Output IO AG17
GPIO0_35 General Purpose Input/Output IO AF17
GPIO0_36 General Purpose Input/Output IO AE17
GPIO0_37 General Purpose Input/Output IO AC19
GPIO0_38 General Purpose Input/Output IO AH16
GPIO0_39 General Purpose Input/Output IO AG16
GPIO0_40 General Purpose Input/Output IO AF16
GPIO0_41 General Purpose Input/Output IO AE16
GPIO0_42 General Purpose Input/Output IO AD16
GPIO0_43 General Purpose Input/Output IO AH15
GPIO0_44 General Purpose Input/Output IO AC16
GPIO0_45 General Purpose Input/Output IO AD17
GPIO0_46 General Purpose Input/Output IO AH14
GPIO0_47 General Purpose Input/Output IO AG14
GPIO0_48 General Purpose Input/Output IO AG15
GPIO0_49 General Purpose Input/Output IO AC17
GPIO0_50 General Purpose Input/Output IO AE15
GPIO0_51 General Purpose Input/Output IO AD15
GPIO0_52 General Purpose Input/Output IO AF14
GPIO0_53 General Purpose Input/Output IO AC15
GPIO0_54 General Purpose Input/Output IO AD14
GPIO0_55 General Purpose Input/Output IO AE14
GPIO0_56 General Purpose Input/Output IO AE22
GPIO0_57 General Purpose Input/Output IO AG24
GPIO0_58 General Purpose Input/Output IO AF23
GPIO0_59 General Purpose Input/Output IO AD21
GPIO0_60 General Purpose Input/Output IO AG23
GPIO0_61 General Purpose Input/Output IO AF27
GPIO0_62 General Purpose Input/Output IO AF22
GPIO0_63 General Purpose Input/Output IO AG27
GPIO0_64 General Purpose Input/Output IO AF28
GPIO0_65 General Purpose Input/Output IO AF26
GPIO0_66 General Purpose Input/Output IO AH25
GPIO0_67 General Purpose Input/Output IO AF21
GPIO0_68 General Purpose Input/Output IO AH20
GPIO0_69 General Purpose Input/Output IO AH21
GPIO0_70 General Purpose Input/Output IO AG20
GPIO0_71 General Purpose Input/Output IO AD19
GPIO0_72 General Purpose Input/Output IO AD20
GPIO0_73 General Purpose Input/Output IO AH26
GPIO0_74 General Purpose Input/Output IO AG25
GPIO0_75 General Purpose Input/Output IO AG26
GPIO0_76 General Purpose Input/Output IO AH24
GPIO0_77 General Purpose Input/Output IO AH23
GPIO0_78 General Purpose Input/Output IO AG21
GPIO0_79 General Purpose Input/Output IO AH22
GPIO0_80 General Purpose Input/Output IO AE21
GPIO0_81 General Purpose Input/Output IO AC22
GPIO0_82 General Purpose Input/Output IO AG22
GPIO0_83 General Purpose Input/Output IO AD23
GPIO0_84 General Purpose Input/Output IO AE24
GPIO0_85 General Purpose Input/Output IO AF25
GPIO0_86 General Purpose Input/Output IO AF24
GPIO0_87 General Purpose Input/Output IO AC20
GPIO0_88 General Purpose Input/Output IO AE20
GPIO0_89 General Purpose Input/Output IO AF19
GPIO0_90 General Purpose Input/Output IO AH19
GPIO0_91 General Purpose Input/Output IO AG19
GPIO0_92 General Purpose Input/Output IO AE19
GPIO0_93 General Purpose Input/Output IO AE23
GPIO0_94 General Purpose Input/Output IO AD22
GPIO0_95 General Purpose Input/Output IO AC21

Table 4-25 GPIO1 Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ACD [4]
GPIO1_0 General Purpose Input/Output IO AD18
GPIO1_1 General Purpose Input/Output IO AH18
GPIO1_2 General Purpose Input/Output IO D25
GPIO1_3 General Purpose Input/Output IO B26
GPIO1_4 General Purpose Input/Output IO A24
GPIO1_5 General Purpose Input/Output IO E24
GPIO1_6 General Purpose Input/Output IO A25
GPIO1_7 General Purpose Input/Output IO C26
GPIO1_8 General Purpose Input/Output IO E25
GPIO1_9 General Purpose Input/Output IO A26
GPIO1_10 General Purpose Input/Output O B25
GPIO1_11 General Purpose Input/Output IO B27
GPIO1_12 General Purpose Input/Output I C25
GPIO1_13 General Purpose Input/Output IO(1) A23
GPIO1_14 General Purpose Input/Output IO(1) B23
GPIO1_15 General Purpose Input/Output IO AG13
GPIO1_16 General Purpose Input/Output IO AF13
GPIO1_17 General Purpose Input/Output IO AH13
GPIO1_18 General Purpose Input/Output IO AE13
GPIO1_19 General Purpose Input/Output IO AD13
GPIO1_20 General Purpose Input/Output IO AD12
GPIO1_21 General Purpose Input/Output IO AG12
GPIO1_22 General Purpose Input/Output IO AH12
GPIO1_23 General Purpose Input/Output IO AE12
GPIO1_24 General Purpose Input/Output IO AF12
GPIO1_25 General Purpose Input/Output IO AF11
GPIO1_26 General Purpose Input/Output IO AE11
GPIO1_27 General Purpose Input/Output IO AG11
GPIO1_28 General Purpose Input/Output IO AD11
GPIO1_29 General Purpose Input/Output IO V24
GPIO1_30 General Purpose Input/Output IO W25
GPIO1_31 General Purpose Input/Output IO W24
GPIO1_32 General Purpose Input/Output IO AA27
GPIO1_33 General Purpose Input/Output IO Y24
GPIO1_34 General Purpose Input/Output IO V28
GPIO1_35 General Purpose Input/Output IO Y25
GPIO1_36 General Purpose Input/Output IO U27
GPIO1_37 General Purpose Input/Output IO V27
GPIO1_38 General Purpose Input/Output IO V26
GPIO1_39 General Purpose Input/Output IO U25
GPIO1_40 General Purpose Input/Output IO AB25
GPIO1_41 General Purpose Input/Output IO AD27
GPIO1_42 General Purpose Input/Output IO AC26
GPIO1_43 General Purpose Input/Output IO AD26
GPIO1_44 General Purpose Input/Output IO AA24
GPIO1_45 General Purpose Input/Output IO AD28
GPIO1_46 General Purpose Input/Output IO U26
GPIO1_47 General Purpose Input/Output IO V25
GPIO1_48 General Purpose Input/Output IO U24
GPIO1_49 General Purpose Input/Output IO AB28
GPIO1_50 General Purpose Input/Output IO AC28
GPIO1_51 General Purpose Input/Output IO AC27
GPIO1_52 General Purpose Input/Output IO AB26
GPIO1_53 General Purpose Input/Output IO AA25
GPIO1_54 General Purpose Input/Output IO U23
GPIO1_55 General Purpose Input/Output IO AB27
GPIO1_56 General Purpose Input/Output IO W28
GPIO1_57 General Purpose Input/Output IO W27
GPIO1_58 General Purpose Input/Output IO Y28
GPIO1_59 General Purpose Input/Output IO AA28
GPIO1_60 General Purpose Input/Output IO AB24
GPIO1_61 General Purpose Input/Output IO AC25
GPIO1_62 General Purpose Input/Output IO AD25
GPIO1_63 General Purpose Input/Output IO AD24
GPIO1_64 General Purpose Input/Output IO AE27
GPIO1_65 General Purpose Input/Output IO AC24
GPIO1_66 General Purpose Input/Output IO Y27
GPIO1_67 General Purpose Input/Output IO Y26
GPIO1_68 General Purpose Input/Output IO W26
GPIO1_69 General Purpose Input/Output IO AE26
GPIO1_70 General Purpose Input/Output IO AE28
GPIO1_71 General Purpose Input/Output IO AD9
GPIO1_72 General Purpose Input/Output IO AC8
GPIO1_73 General Purpose Input/Output IO D27
GPIO1_74 General Purpose Input/Output IO D26
GPIO1_75 General Purpose Input/Output IO E27
GPIO1_76 General Purpose Input/Output IO D28
GPIO1_77 General Purpose Input/Output O C27
GPIO1_78 General Purpose Input/Output IO C28
GPIO1_79 General Purpose Input/Output IO(1) B24
GPIO1_80 General Purpose Input/Output IO(1) C24
GPIO1_86 General Purpose Input/Output IO D21
GPIO1_87 General Purpose Input/Output IO A22
GPIO1_88 General Purpose Input/Output IO B22
GPIO1_89 General Purpose Input/Output IO C23
  1. When OSC1 is being used with an external crystal, this pin must only be used as an input. The output functionality must be disabled.