ZHCSNB0D february   2021  – june 2023 AFE7950

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4说明（续）
  6. 5Revision History
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Transmitter Electrical Characteristics
    6. 6.6  RF ADC Electrical Characteristics
    7. 6.7  PLL/VCO/Clock Electrical Characteristics
    8. 6.8  Digital Electrical Characteristics
    9. 6.9  Power Supply Electrical Characteristics
    10. 6.10 Timing Requirements
    11. 6.11 Switching Characteristics
    12. 6.12 Typical Characteristics
      1. 6.12.1  TX Typical Characteristics 800 MHz
      2. 6.12.2  TX Typical Characteristics at 1.8 GHz
      3. 6.12.3  TX Typical Characteristics at 2.6 GHz
      4. 6.12.4  TX Typical Characteristics at 3.5 GHz
      5. 6.12.5  TX Typical Characteristics at 4.9 GHz
      6. 6.12.6  TX Typical Characteristics at 8.1 GHz
      7. 6.12.7  TX Typical Characteristics at 9.6 GHz
      8. 6.12.8  RX Typical Characteristics at 800 MHz
      9. 6.12.9  RX Typical Characteristics at 1.75 GHz – 1.9 GHz
      10. 6.12.10 RX Typical Characteristics at 2.6 GHz
      11. 6.12.11 RX Typical Characteristics at 3.5 GHz
      12. 6.12.12 RX Typical Characteristics at 4.9 GHz
      13. 6.12.13 RX Typical Characteristics at 8.1GHz
      14. 6.12.14 RX Typical Characteristics at 9.6 GHz
      15. 6.12.15 PLL and Clock Typical Characteristics
  8. 7Device and Documentation Support
    1. 7.1 接收文档更新通知
    2. 7.2 支持资源
    3. 7.3 商标
    4. 7.4 静电放电警告
    5. 7.5 术语表
  9. 8Mechanical, Packaging, and Orderable Information

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6.12.2 TX Typical Characteristics at 1.8 GHz

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled

GUID-8C29C0AB-91CD-44B1-919A-4FAAFE568301-low.gif
including PCB and cable losses, Aout = -0.5dFBS, DSA = 0, 1.8 GHz matching
Figure 6-44 TX Output Fullscale vs Output Frequency
GUID-31400215-312E-42B5-86F3-12DBAC10E7A2-low.gif
fDAC=5898.24MSPS, interleave mode, matching at 1.8 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1
Figure 6-46 TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 1.8 GHz
GUID-32A36896-22F2-4588-BFB4-9A3826EFCF5F-low.gif
fDAC=5898.24MSPS, interleave mode, matching at 1.8 GHz
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)
Figure 6-48 TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 1.8 GHz
GUID-4D62AE58-26B6-44C3-82D9-C5A812551A79-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1
Figure 6-50 TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 1.8 GHz
GUID-76AA1407-8E4B-4C6A-81CB-CB75BC66596D-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)
Figure 6-52 TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 1.8 GHz
GUID-C243D5C7-1C9F-4EFC-BE11-3AADBB370844-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)
Figure 6-54 TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 1.8 GHz
GUID-80CD381E-897F-4629-902C-530FD773DAA0-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 6-56 TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 1.8 GHz
GUID-EE8467E6-2061-4F53-A27B-FE98862D0E68-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)
Figure 6-58 TX Uncalibrated Differential Phase Error vs DSA Setting and Temperature at 1.8 GHz
GUID-2BA5B0C7-6C3C-4661-BD44-A16455ECE879-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz, channel with the median variation over DSA setting at 25°C
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 6-60 TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 1.8 GHz
GUID-101AF4C6-437B-4667-B2F0-430880F7D239-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz, POUT = –13 dBFS
Figure 6-62 TX Output Noise vs Channel and Attenuation at 1.8 GHz
GUID-75F70737-6CB2-49E9-92FA-54ECAFE13401-low.gif
fDAC = 11796.48MSPS, interleave mode, fCENTER = 1.8 GHz, matching at 1.8 GHz, –13 dBFS each tone
Figure 6-64 TX IMD3 vs Tone Spacing and Channel at 1.8 GHz
GUID-6859C313-BD69-4FD7-9786-9EF1F311EA0C-low.gif
fDAC = 11796.48MSPS, interleave mode, fCENTER = 1.8 GHz, fSPACING = 20 MHz, matching at 1.8 GHz
Figure 6-66 TX IMD3 vs Digital Level at 1.8 GHz
GUID-FE913DD7-0F02-4C81-8AAC-D03B329DB8F9-low.gif
TM1.1, POUT_RMS = –13 dBFS
Figure 6-68 TX 20-MHz LTE Output Spectrum at 1.8425 GHz
GUID-746DE7E8-3C80-4B29-98AF-C85F7723B297-low.gif
Matching at 1.8 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-70 TX 20-MHz LTE alt-ACPR vs Digital Level at 1.8425 GHz
GUID-AFC77E71-9C54-4504-86CB-02E7CDF68FFB-low.gif
Matching at 1.8 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-72 TX 20-MHz LTE alt-ACPR vs DSA at 1.8 GHz
GUID-EB8F4BCD-2D22-4F44-90EE-C4751EBDE752-low.gif
Matching at 1.8 GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency
Figure 6-74 TX HD3 vs Digital Amplitude and Output Frequency at 1.8 GHz
GUID-A4A4B013-1134-4106-9AC7-5E1B8CDABEEC-low.gif
fDAC = 8847.36MSPS, straight mode, 1.8 GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT and is due to mixing with digital clocks.
Figure 6-76 TX Single Tone (–6 dBFS) Output Spectrum at 1.8 GHz (0-fDAC)
GUID-980CB847-ECD0-4287-9797-588ADD61D1C6-low.gif
Aout = -0.5dFBS, matching 1.8 GHz
Figure 6-45 TX Output Power vs Temperature at 1.8 GHz
GUID-2916429E-028A-4AAF-9F68-63E331BA0A45-low.gif
fDAC=5898.24MSPS, interleave mode, matching at 1.8 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1
Figure 6-47 TX Calibrated Differential Gain Error vs DSA Setting and Channel at 1.8 GHz
GUID-13FFB36E-16D6-421E-8348-040806506A28-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)
Figure 6-49 TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 1.8 GHz
GUID-A6DFD3C0-4C81-494D-8C6F-EA7D0CECE1E2-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1
Figure 6-51 TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 1.8 GHz
GUID-7F071E5E-C357-46DA-A2CA-720DCE9AB557-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)
Figure 6-53 TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 1.8 GHz
GUID-F973ED55-9DEB-4B05-99B2-9C956F356018-low.gif
fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)
Phase DNL spike may occur at any DSA setting.
Figure 6-55 TX Calibrated Differential Phase Error vs DSA Setting and Channel at 1.8 GHz
GUID-775B32AE-AB2D-45A1-8D7E-7ED321F95134-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 6-57 TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 1.8 GHz
GUID-6113A9A4-4612-4029-A4E6-5ABFC6F09515-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz, channel with the median variation over DSA setting at 25°C
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)
Figure 6-59 TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 1.8 GHz
GUID-73EE48FE-8100-46E1-87AA-060C71D1C804-low.gif
fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz, channel with the median variation over DSA setting at 25°C
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 6-61 TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 1.8 GHz
GUID-C4C45129-EE86-4A4F-8E8E-4BD675CE5A01-low.gif
fDAC = 11796.48MSPS, interleave mode, fCENTER = 1.8 GHz, matching at 1.8 GHz, –13 dBFS each tone
Figure 6-63 TX IMD3 vs DSA Setting at 1.8 GHz
GUID-F42EDD78-A334-4858-B166-0D3FE9D61B84-low.gif
fDAC = 11796.48MSPS, interleave mode, fCENTER = 1.8 GHz, matching at 1.8 GHz, –13 dBFS each tone, worst channel
Figure 6-65 TX IMD3 vs Tone Spacing and Temperature at 1.8 GHz
GUID-C4C59BF2-01C9-4944-9F8A-CA5016168261-low.gif
Matching at 2.6 GHz, Single tone, fDAC = 11.79648GSPS, interleave mode, 40-MHz offset
Figure 6-67 TX Single Tone Output Noise vs Frequency and Amplitude at 1.8 GHz
GUID-F71919D1-F695-4DEE-9003-23E87F3F47EF-low.gif
Matching at 1.8 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-69 TX 20-MHz LTE ACPR vs Digital Level at 1.8425 GHz
GUID-673BFA61-85A0-4D92-A963-B6B5149242AF-low.gif
Matching at 1.8 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-71 TX 20-MHz LTE ACPR vs DSA at 1.8 GHz
GUID-B1150E72-3C49-4803-9F6E-0124800FDD5A-low.gif
Matching at 1.8 GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency
Figure 6-73 TX HD2 vs Digital Amplitude and Output Frequency at 1.8 GHz
GUID-5F7B77DD-CF6A-49F4-83EB-F117E4FA43E0-low.gif
fDAC = 8847.36MSPS, straight mode, 1.8 GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT and is due to mixing with digital clocks.
Figure 6-75 TX Single Tone (–12 dBFS) Output Spectrum at 1.8 GHz (0-fDAC)
GUID-6B5BC7B2-C6C2-4635-92A2-77A24B281B9B-low.gif
fDAC = 8847.36MSPS, straight mode, 1.8 GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT and is due to mixing with digital clocks.
Figure 6-77 TX Single Tone (–1 dBFS) Output Spectrum at 1.8 GHz (0-fDAC)