ZHCSDS3C May   2015  – April 2018 ADS52J90

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Digital Characteristics
    7. 7.7  Timing Requirements: Signal Chain
    8. 7.8  Timing Requirements: JESD Interface
    9. 7.9  Timing Requirements: Serial Interface
    10. 7.10 Typical Characteristics
    11. 7.11 Typical Characteristics: JESD Interface
    12. 7.12 Typical Characteristics: Contour Plots
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Connection of the External Inputs to the Input Pins
      2. 8.3.2  Input Multiplexer and Sampler
      3. 8.3.3  Analog-to-Digital Converter (ADC)
      4. 8.3.4  Device Synchronization Using TX_TRIG
      5. 8.3.5  Digital Processing
        1. 8.3.5.1 Digital Offset
          1. 8.3.5.1.1 Manual Offset Correction
          2. 8.3.5.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)
          3. 8.3.5.1.3 Digital Averaging
          4. 8.3.5.1.4 Digital Gain
          5. 8.3.5.1.5 Digital HPF
      6. 8.3.6  Data Formatting
      7. 8.3.7  Serializer and LVDS Interface
      8. 8.3.8  LVDS Buffers
      9. 8.3.9  JESD204B Interface
        1. 8.3.9.1 Overview
        2. 8.3.9.2 Link Configuration
        3. 8.3.9.3 JESD Version and Subclass
        4. 8.3.9.4 Transport Layer
          1. 8.3.9.4.1 User Data Format
          2. 8.3.9.4.2 Transport Layer Test Patterns
        5. 8.3.9.5 Scrambler
        6. 8.3.9.6 Data Link Layer
          1. 8.3.9.6.1 Code Group Synchronization (CGS)
          2. 8.3.9.6.2 Initial Lane Alignment (ILA)
          3. 8.3.9.6.3 Lane and Frame Alignment Monitoring
          4. 8.3.9.6.4 Link Layer Test Modes
        7. 8.3.9.7 Deterministic Latency
          1. 8.3.9.7.1 Synchronization Using SYNC~ and SYSREF
          2. 8.3.9.7.2 Latency
          3. 8.3.9.7.3 Multiframe Size
        8. 8.3.9.8 JESD Physical Layer
          1. 8.3.9.8.1 CML Buffer
          2. 8.3.9.8.2 Jitter Considerations
      10. 8.3.10 Interfacing SYNC~ and SYSREF Between the FPGA and ADCs
      11. 8.3.11 Clock Input
      12. 8.3.12 Analog Input and Driving Circuit
        1. 8.3.12.1 Signal Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Modes
      2. 8.4.2 ADC Resolution Modes
      3. 8.4.3 LVDS and JESD Interface Modes
      4. 8.4.4 LVDS Serialization and Output Data Rate Modes
      5. 8.4.5 Power Modes
      6. 8.4.6 LVDS Test Pattern Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Operation
        1. 8.5.1.1 Serial Register Write Description
        2. 8.5.1.2 Register Readout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing with the 16-Input Mode
        2. 9.2.2.2 Designing with the 32-Input Mode
        3. 9.2.2.3 Designing with the 8-Input Mode
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Power Supply, Grounding, and Bypassing
    2. 11.2 Layout Guidelines
    3. 11.3 Layout Example
  12. 12Register Map
    1. 12.1 ADC Registers
      1. 12.1.1 Description of Registers
        1. 12.1.1.1  Register 0h (address = 0h)
          1. Table 47. Register 0h Field Descriptions
        2. 12.1.1.2  Register 1h (address = 1h)
          1. Table 48. Register 1h Field Descriptions
        3. 12.1.1.3  Register 2h (address = 2h)
          1. Table 51. Register 2h Field Descriptions
        4. 12.1.1.4  Register 3h (address = 3h)
          1. Table 53. Register 3h Field Descriptions
        5. 12.1.1.5  Register 4h (address = 4h)
          1. Table 54. Register 4h Field Descriptions
        6. 12.1.1.6  Register 5h (address = 5h)
          1. Table 55. Register 5h Field Descriptions
        7. 12.1.1.7  Register 7h (address = 7h)
          1. Table 56. Register 7h Field Descriptions
        8. 12.1.1.8  Register 8h (address = 8h)
          1. Table 57. Register 8h Field Descriptions
        9. 12.1.1.9  Register Ah (address = Ah)
          1. Table 58. Register Ah Field Descriptions
        10. 12.1.1.10 Register Bh (address = Bh)
          1. Table 59. Register Bh Field Descriptions
        11. 12.1.1.11 Register Dh (address = Dh)
          1. Table 60. Register Dh Field Descriptions
        12. 12.1.1.12 Register Eh (address = Eh)
          1. Table 61. Register Eh Field Descriptions
        13. 12.1.1.13 Register Fh (address = Fh)
          1. Table 62. Register Fh Field Descriptions
        14. 12.1.1.14 Register 10h (address = 10h)
          1. Table 63. Register 10h Field Descriptions
        15. 12.1.1.15 Register 11h (address = 11h)
          1. Table 64. Register 11h Field Descriptions
        16. 12.1.1.16 Register 12h (address = 12h)
          1. Table 65. Register 12h Field Descriptions
        17. 12.1.1.17 Register 13h (address = 13h)
          1. Table 66. Register 13h Field Descriptions
        18. 12.1.1.18 Register 14h (address = 14h)
          1. Table 67. Register 14h Field Descriptions
        19. 12.1.1.19 Register 15h (address = 15h)
          1. Table 68. Register 15h Field Descriptions
        20. 12.1.1.20 Register 17h (address = 17h)
          1. Table 69. Register 17h Field Descriptions
        21. 12.1.1.21 Register 18h (address = 18h)
          1. Table 70. Register 18h Field Descriptions
        22. 12.1.1.22 Register 19h (address = 19h)
          1. Table 71. Register 19h Field Descriptions
        23. 12.1.1.23 Register 1Ah (address = 1Ah)
          1. Table 72. Register 1Ah Field Descriptions
        24. 12.1.1.24 Register 1Bh (address = 1Bh)
          1. Table 73. Register 1Bh Field Descriptions
        25. 12.1.1.25 Register 1Ch (address = 1Ch)
          1. Table 74. Register 1Ch Field Descriptions
        26. 12.1.1.26 Register 1Dh (address = 1Dh)
          1. Table 75. Register 1Dh Field Descriptions
        27. 12.1.1.27 Register 1Eh (address = 1Eh)
          1. Table 76. Register 1Eh Field Descriptions
        28. 12.1.1.28 Register 1Fh (address = 1Fh)
          1. Table 77. Register 1Fh Field Descriptions
        29. 12.1.1.29 Register 20h (address = 20h)
          1. Table 78. Register 20h Field Descriptions
        30. 12.1.1.30 Register 21h (offset = 21h)
          1. Table 79. Register 21h Field Descriptions
        31. 12.1.1.31 Register 23h (register = 23h)
          1. Table 80. Register 23h Field Descriptions
        32. 12.1.1.32 Register 24h (address = 24h)
          1. Table 81. Register 24h Field Descriptions
        33. 12.1.1.33 Register 25h (address = 25h)
          1. Table 82. Register 25h Field Descriptions
        34. 12.1.1.34 Register 26h (address = 26h)
          1. Table 83. Register 26h Field Descriptions
        35. 12.1.1.35 Register 27h (address = 27h)
          1. Table 84. Register 27h Field Descriptions
        36. 12.1.1.36 Register 28h (address = 28h)
          1. Table 85. Register 28h Field Descriptions
        37. 12.1.1.37 Register 29h (address = 29h)
          1. Table 86. Register 29h Field Descriptions
        38. 12.1.1.38 Register 2Ah (address = 2Ah)
          1. Table 87. Register 2Ah Field Descriptions
        39. 12.1.1.39 Register 2Bh (address = 2Bh)
          1. Table 88. Register 2Bh Field Descriptions
        40. 12.1.1.40 Register 2Ch (address = 2Ch)
          1. Table 89. Register 2Ch Field Descriptions
        41. 12.1.1.41 Register 2Dh (address = 2Dh)
          1. Table 90. Register 2Dh Field Descriptions
        42. 12.1.1.42 Register 2Fh (address = 2Fh)
          1. Table 91. Register 2Fh Field Descriptions
        43. 12.1.1.43 Register 30h (address = 30h)
          1. Table 92. Register 30h Field Descriptions
        44. 12.1.1.44 Register 31h (address = 31h)
          1. Table 93. Register 31h Field Descriptions
        45. 12.1.1.45 Register 32h (address = 32h)
          1. Table 94. Register 32h Field Descriptions
        46. 12.1.1.46 Register 33h (address = 33h)
          1. Table 95. Register 33h Field Descriptions
        47. 12.1.1.47 Register 34h (address = 34h)
          1. Table 96. Register 34h Field Descriptions
        48. 12.1.1.48 Register 35h (address = 35h)
          1. Table 97. Register 35h Field Descriptions
        49. 12.1.1.49 Register 36h (address = 36h)
          1. Table 98. Register 36h Field Descriptions
        50. 12.1.1.50 Register 37h (address = 37h)
          1. Table 99. Register 37h Field Descriptions
        51. 12.1.1.51 Register 38h (address = 38h)
          1. Table 100. Register 38h Field Descriptions
        52. 12.1.1.52 Register 39h (address = 39h)
          1. Table 101. Register 39h Field Descriptions
        53. 12.1.1.53 Register 3Bh (address = 3Bh)
          1. Table 102. Register 3Bh Field Descriptions
        54. 12.1.1.54 Register 3Ch (address = 3Ch)
          1. Table 103. Register 3Ch Field Descriptions
        55. 12.1.1.55 Register 43h (address = 43h)
          1. Table 104. Register 43h Field Descriptions
    2. 12.2 JESD Serial Interface Registers
      1. 12.2.1 Description of JESD Serial Interface Registers
        1. 12.2.1.1  Register 70 (address = 46h)
          1. Table 106. Register 70 Field Descriptions
        2. 12.2.1.2  Register 73 (address = 49h)
          1. Table 107. Register 73 Field Descriptions
        3. 12.2.1.3  Register 74 (address = 4Ah)
          1. Table 108. Register 74 Field Descriptions
        4. 12.2.1.4  Register 75 (address = 4Bh)
          1. Table 109. Register 75 Field Descriptions
        5. 12.2.1.5  Register 77 (address = 4Dh)
          1. Table 110. Register 77 Field Descriptions
        6. 12.2.1.6  Register 80 (address = 50h)
          1. Table 111. Register 80 Field Descriptions
        7. 12.2.1.7  Register 81 (address = 51h)
          1. Table 112. Register 81 Field Descriptions
        8. 12.2.1.8  Register 82 (address = 52h)
          1. Table 113. Register 82 Field Descriptions
        9. 12.2.1.9  Register 83 (address = 53h)
          1. Table 114. Register 83 Field Descriptions
        10. 12.2.1.10 Register 85 (address = 55h)
          1. Table 115. Register 85 Field Descriptions
        11. 12.2.1.11 Register 115 (address = 73h)
          1. Table 116. Register 115 Field Descriptions
        12. 12.2.1.12 Register 116 (address = 74h)
          1. Table 117. Register 116 Field Descriptions
        13. 12.2.1.13 Register 117 (address = 75h)
          1. Table 118. Register 117 Field Descriptions
        14. 12.2.1.14 Register 118 (address = 76h)
          1. Table 119. Register 118 Field Descriptions
        15. 12.2.1.15 Register 119 (address = 77h)
          1. Table 120. Register 119 Field Descriptions
        16. 12.2.1.16 Register 120 (address = 78h)
          1. Table 121. Register 120 Field Descriptions
        17. 12.2.1.17 Register 134 (address = 86h)
          1. Table 122. Register 134 Field Descriptions
        18. 12.2.1.18 Register 135 (address = 87h)
          1. Table 123. Register 135 Field Descriptions
        19. 12.2.1.19 Register 136 (address = 88h)
          1. Table 124. Register 136 Field Descriptions
        20. 12.2.1.20 Register 137 (address = 89h)
          1. Table 125. Register 137 Field Descriptions
        21. 12.2.1.21 Register 138 (address = 8Ah)
          1. Table 126. Register 138 Field Descriptions
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • ZZE|198
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.2.3 Application Curves

This section outlines the trends described in the Typical Characteristics section from an application perspective.

Figure 2 illustrates the FFT with a 5-MHz input signal for 32-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 3 illustrates the FFT with a 5-MHz input signal for 16-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 100 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 4 illustrates the FFT with a 5-MHz input signal for 8-input mode with the ADC resolution set to 10 bits. The system clock provided is 200 MSPS and the input is sampled at an effective rate of 200 MSPS, which is the maximum sampling rate for this mode of operation. The increase in sampling rate is achieved through two ADCs converting the same input in an interleaved manner. The interleaving spurs are visible in the FFT. The predominant spur is at the frequencies of (fS / 2 ± fIN), which appear at 95 MHz. Additional spurs are at the frequencies of (fS / 4 ± fIN), which appear at 45 MHz and 55 MHz. The magnitude of the spurs is expected to rise when the input frequency is increased. Also, the spur level is sensitive to the matching of the manner in which the two sets of input pins are driven. A spur at fS/4 is also seen. This arises from the offset mismatch between the four sets of sampling circuits used to sample the same input.

Figure 5 illustrates the FFT with a 5-MHz input signal for 32-input mode with the ADC resolution set to 12 bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 40 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 6 illustrates the FFT with a 5-MHz input signal for 16-input mode with the ADC resolution set to 12 bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 80 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 7 illustrates the FFT with a 5-MHz input signal for 32-input mode with the ADC resolution set to 14 bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 32.5 MSPS, which is the maximum sampling rate for this mode of operation.

Figure 8 illustrates the FFT with a 5-MHz input signal for 16-input mode with the ADC resolution set to 14 bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 65 MSPS, which is the maximum sampling rate for this mode of operation. In addition to the harmonics, the spur at the frequency (fS / 2 ± fIN) also occurs at 27.5 MHz. This spur is caused by the interleaved sampling of the input signal by two physically different sampling circuits of the same ADC.

Figure 9 illustrates the signal-to-noise ratio (SNR) versus the frequency of the input signal for 32-input mode with the ADC resolution set to 10 bits. SNR is expressed in the dBFS scale where the RMS noise at the ADC output is referred to the full-scale differential voltage of 2 V. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. SNR is computed by integrating the noise in all FFT bins after excluding the first nine harmonics. SNR is dominated by the quantization noise of the 10-bit conversion.

Figure 10 illustrates SNR versus the frequency of the input signal for 16-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 100 MSPS. SNR is computed by integrating the noise in all FFT bins after excluding the first nine harmonics and any interleaving spurs. SNR is dominated by the quantization noise of the 10-bit conversion.

Figure 11 illustrates SNR versus the frequency of the input signal for 8-input mode with the ADC resolution set to 10 bits. The system clock provided is 200 MSPS and the input is sampled at an effective rate of 200 MSPS. SNR is computed by integrating the noise in all FFT bins after excluding the first nine harmonics and any interleaving spurs at (fS / 2 ± fIN) and (fS / 4 ± fIN) as well as additional spurs at fS / 2 and fS / 4. SNR is dominated by the quantization noise of the 10-bit conversion.

Figure 12 illustrates SNR versus the frequency of the input signal for 32-input mode with the ADC resolution set to 12 bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 40 MSPS.

Figure 13 illustrates SNR versus the frequency of the input signal for 16-input mode with the ADC resolution set to 12 bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 80 MSPS.

Figure 14 illustrates SNR versus the frequency of the input signal for 32-input mode with the ADC resolution set to 14 bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 32.5 MSPS. SNR at high input frequencies degrades because of clock jitter.

Figure 15 illustrates SNR versus the frequency of the input signal for 16-input mode with the ADC resolution set to 14 bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 65 MSPS.

Figure 16 illustrates the amplitude of the third-order harmonic distortion (HD3) of the input signal versus the frequency of the input signal. The unit of dBc indicates that the HD3 amplitude is referred to the amplitude of the input signal, which is set to –1 dBFS. Figure 16 is taken for 32-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. The device follows a similar trend across the other input modes and resolutions.

Figure 17 illustrates the amplitude of the second-order harmonic distortion (HD2) of the input signal versus the frequency of the input signal. The unit of dBc indicates that the HD2 amplitude is referred to the amplitude of the input signal, which is set to –1 dBFS. Figure 17 is taken for 32-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. The device follows a similar trend across the other input modes and resolutions.

Figure 18 illustrates the total harmonic distortion (THD) versus the frequency of the input signal. The THD parameter includes the RMS amplitude of the first nine harmonics of the fundamental signal. The unit of dBc indicates that THD is referred to the amplitude of the input signal, which is set to –1 dBFS. Figure 18 is taken for 32-input mode with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. The device follows a similar trend across the other input modes and resolutions.

Figure 19 illustrates the interleaving spur at (fS / 2 ± fIN) versus the frequency of the input signal. Figure 19 is taken for 8-input mode with the ADC resolution set to 10 bits. The system clock is set to 200 MSPS and the input is sampled at an effective rate of 200 MSPS. The interleaving spur at (fS / 2 ± fIN) is referred to the fundamental amplitude, which is at a level of –1 dBFS. The (fS / 2 ± fIN) spur comes about because of the interleaved conversion of the same input by two ADCs. As illustrated in Figure 19, the interleaving spur gets much worse at higher input frequencies. This degradation results from the fact that when the input frequency is increased, any mismatch in the sampling bandwidths and sampling instants of the two interleaved ADCs leads to a larger phase error between the interleaved conversions.

Figure 20 illustrates the interleaving spur at (fS / 2 ± fIN) versus the frequency of the input signal. Figure 20 is taken for 16-input mode with the ADC resolution set to 10 bits. The system clock is set to 100 MSPS and the input is sampled at an effective rate of 100 MSPS. The (fS / 2 ± fIN) spur comes about because of the interleaved sampling of the input by the two sampling circuits of one ADC. Although not as bad as the (fS / 2 ± fIN) spur for 8-input mode, the interleaving spur could still be the dominant factor governing the SFDR at high input frequencies.

Figure 21 illustrates the interleaving spur at (fS / 4 ± fIN) versus the frequency of the input signal. Figure 21 is taken for 8-input mode with the ADC resolution set to 10 bits. The system clock is set to 200 MSPS and the input is sampled at an effective rate of 200 MSPS. In 8-input mode, there are a total of four sampling circuits (two in each ADC) that sample the same input in sequence. The (fS / 4 ± fIN) spur comes about from mismatches between these four sampling circuits.

Figure 22 illustrates SNR in dBFS as a function of the input amplitude, also expressed in dBFS. SNR excludes the first nine harmonics and the interleaving spurs. Figure 22 is taken for the 16-input mode with the ADC resolution set to 14 bits. The system clock is set to 65 MSPS and the input is sampled at an effective rate of 65 MSPS. The points in the left extreme of the curve provide an estimate of the idle channel SNR (SNR in the absence of an input signal).

Figure 23 illustrates the spurious-free dynamic range (SFDR) as a function of the input amplitude. Figure 23 is taken for 32-input mode with the ADC resolution set to 14 bits. In 32-input mode, there is no interleaved operation of any sort and SFDR is a true measure of ADC conversion performance. As mentioned previously, SFDR may be dominated by interleaving spurs (and significantly lower than 32-input mode) when operated in 16-input or 8-input modes. SFDR is plotted in both dBc and dBFS: the former referring the amplitude of the worst-spur to the fundamental amplitude and the latter to the full-scale voltage.

Figure 24 illustrates SNR as a function of the input common-mode voltage (average of INP and INM). Figure 24 is taken for 16-input mode with the ADC resolution set to 14 bits. The device is meant to be operated at an input common-mode that is tightly controlled around the ideal value of 0.8 V. The driving circuit can generate its output common-mode using the 0.8-V reference voltage provided at the VCM pin.

Figure 25 illustrates SNR as a function of the input clock amplitude (expressed in differential VPP) when driven with a differential sine-wave clock input. At small input amplitudes, the sine-wave clock has a low dV/dt slope at the zero crossings. This low slope can cause increased jitter in the clocking and can lead to a reduction in the SNR within the device. The effect is more pronounced when the input frequency is set to a higher value (as is evidenced by the difference in behavior between the 5-MHz and 50-MHz inputs). The recommended manner to drive the device is with an LVPECL clock.

Figure 26 illustrates SNR as a function of the duty cycle of a differential clock input. Ideally, the device is driven with a 50% clock; see the Electrical Characteristics table for the acceptable variation around 50% duty cycle.

Figure 27 illustrates the channel-to-channel crosstalk as a function of the analog input frequency. An analog input of a –1-dBFS amplitude is applied on one channel and the crosstalk spur (at the input frequency) is measured on all channels. The worst of the crosstalk numbers (usually on the physically closest channel) is plotted.

Figure 28 illustrates the integral nonlinearity (INL) versus ADC code. The device is operated in 32-input mode at 14-bit resolution with an effective sampling rate of 32.5 MSPS. Figure 28 provides an accurate INL estimate of the ADC inside the device because there is no interleaving of any kind in the 32-input mode operation.

Figure 29 illustrates the differential nonlinearity (DNL) versus ADC code. The device is operated in 32-input mode at 14-bit resolution with an effective sampling rate of 32.5 MSPS. The saturation of the DNL on the lower side to –1 indicates missing codes at the 14-bit level.

Figure 30 illustrates the power-supply rejection ratio (PSRR) as a function of the tone frequency applied on the supply. A tone is applied on the supplies and the tone at the same frequency is measured at the device output. The unit of dBc refers to the relation of the amplitude of the output tone to the amplitude of the supply tone that is set to 100 mVPP for this measurement.

Figure 31 illustrates the power-supply modulation ratio (PSMR) as a function of the tone frequency applied on the supply. A –1-dBFS input at 5 MHz is applied on the analog input. Simultaneously, a 100-mVPP tone is applied on the supply. The tone caused by the intermodulation between the supply tone and the input tone is measured at the device output. PSMR refers to the intermodulation tone referred to in terms of dBc to the amplitude of the input tone.

Figure 32 illustrates the common-mode rejection ratio (CMRR) as a function of the tone frequency applied as a common-mode signal on the input pins. A 50-mVPP common-mode signal is applied to INP and INM around the ideal common-mode voltage of 0.8 V. The amplitude of the tone at the same frequency is measured at the device output. CMRR refers to the amplitude of this output tone referred to in terms of dBc to the amplitude of the common-mode input tone.

Figure 33 illustrates the current of the AVDD_1P8 supply as a function of fC, the conversion clock frequency. The relation of the sampling rate to the conversion clock frequency is different between the 16-, 32-, and 8- input modes and therefore the curve can be appropriately interpreted for each mode. The curve extends to a conversion clock frequency of up to 100 MSPS, which is the maximum value for the 10-bit ADC resolution. For the 12- and 14-bit ADC resolutions, sections of the same curve up to 80 MSPS and 65 MSPS (respectively) are applicable.

Figure 34 illustrates the current of the DVDD_1P8 supply as a function of the conversion clock frequency. All 16 LVDS buffers are on during this measurement.

Figure 35 illustrates the current of the DVDD_1P2 supply as a function of the conversion clock frequency.

Figure 36 illustrates the total power consumption as a function of the conversion clock frequency. The power per input channel can be calculated by dividing this total power by 8, 16, or 32 for the 8-, 16-, or 32-input modes.

Figure 37 illustrates the digital high-pass filter response for different settings of the HPF corner frequency.

Figure 38 illustrates the typical minimum and maximum SNR values taken across 100 devices operating in the 14-bit, 32-input mode at fC = 65 MSPS (corresponding to fSAMP = 32.5 MSPS). A trend can be observed across channels and originates from the physical placement and routing of common signals (such as reference voltage and power) to the channels. Depending on the way the channel data are combined, an averaging effect can result when the system-level SNR is computed.

Figure 39 illustrates a plot of the low-frequency noise from the device with and without the chopper enabled. When the chopper is enabled (using the CHOPPER_EN register control), the low-frequency noise generated inside the device is shifted to approximately fS / 2. Chopper mode is useful when the signal frequency of interest is close to dc.

Figure 48 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 32-input mode operating with a 10-bit ADC resolution.

Figure 49 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 16-input mode operating with a 10-bit ADC resolution.

Figure 50 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 8-input mode operating with a 10-bit ADC resolution.

Figure 51 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 32-input mode operating with a 12-bit ADC resolution.

Figure 52 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 16-input mode operating with a 12-bit ADC resolution.

Figure 53 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 32-input mode operating with a 14-bit ADC resolution.

Figure 54 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 16-input mode operating with a 14-bit ADC resolution.