ZHCSEA6B September   2015  – April 2016 ADS1257

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Serial Interface Timing Requirements
    7. 7.7  Serial Interface Switching Characteristics
    8. 7.8  RESET and SYNC/PWDN Timing Requirements
    9. 7.9  SCLK Reset Timing Requirements
    10. 7.10 DRDY Update Timing Characteristics
    11. 7.11 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Noise Performance
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Input Multiplexer
      2. 9.3.2  Analog Input Buffer
      3. 9.3.3  Programmable Gain Amplifier (PGA)
      4. 9.3.4  Modulator Input Circuitry
      5. 9.3.5  Voltage Reference Inputs (REFP, REFN)
      6. 9.3.6  Clock Input (CLKIN)
      7. 9.3.7  Clock Output (D0/CLKOUT)
      8. 9.3.8  General-Purpose Digital I/O (D0, D1)
      9. 9.3.9  Open- and Short-Circuit Sensor Detection
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Frequency Response
        2. 9.3.10.2 50-Hz and 60-Hz, Line Cycle Rejection
        3. 9.3.10.3 Settling Time
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up
      2. 9.4.2 Reset
      3. 9.4.3 Standby Mode
      4. 9.4.4 Power-Down Mode
      5. 9.4.5 Conversion Control and Synchronization
        1. 9.4.5.1 Settling Time Using Synchronization
        2. 9.4.5.2 Settling Time Using Single-Shot Mode
        3. 9.4.5.3 Settling Time Using the Input Multiplexer
        4. 9.4.5.4 Settling Time while Continuously Converting
      6. 9.4.6 Calibration
        1. 9.4.6.1 Self-Calibration
          1. 9.4.6.1.1 SELFOCAL Command: Self-Offset Calibration
          2. 9.4.6.1.2 SELFGCAL Command: Self-Gain Calibration
          3. 9.4.6.1.3 SELFCAL Command: Self-Offset and Self-Gain Calibration
        2. 9.4.6.2 System Calibration
          1. 9.4.6.2.1 SYSOCAL Command: System-Offset Calibration
          2. 9.4.6.2.2 SYSGCAL Command: System-Gain Calibration
        3. 9.4.6.3 Auto-Calibration
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN) and Data Output (DOUT)
        4. 9.5.1.4 Data Ready (DRDY)
      2. 9.5.2 Data Format
      3. 9.5.3 Command Definitions
        1. 9.5.3.1  WAKEUP/NOP: Complete Synchronization or Exit Standby Mode
        2. 9.5.3.2  RDATA: Read Data
        3. 9.5.3.3  RDATAC: Read Data Continuous
        4. 9.5.3.4  SDATAC: Stop Read Data Continuous
        5. 9.5.3.5  RREG: Read from Registers
        6. 9.5.3.6  WREG: Write to Register
        7. 9.5.3.7  SELFCAL: Self-Offset and Self-Gain Calibration
        8. 9.5.3.8  SELFOCAL: Self Offset Calibration
        9. 9.5.3.9  SELFGCAL: Self Gain Calibration
        10. 9.5.3.10 SYSOCAL: System Offset Calibration
        11. 9.5.3.11 SYSGCAL: System Gain Calibration
        12. 9.5.3.12 STANDBY: Standby Mode / Single-shot Mode
        13. 9.5.3.13 RESET: Reset Registers to Default Values
        14. 9.5.3.14 SYNC: Synchronize the Analog-to-Digital Conversion
    6. 9.6 Register Map
      1. 9.6.1  STATUS: Status Register (address = 00h) [reset = x1h]
      2. 9.6.2  MUX : Input Multiplexer Control Register (address = 01h) [reset = 01h]
      3. 9.6.3  ADCON: ADC Control Register (address = 02h) [reset = 20h]
      4. 9.6.4  DRATE: ADC Data Rate Register (address = 03h) [reset = F0h]
      5. 9.6.5  IO: GPIO Control Register (address = 04h) [reset = E0h]
      6. 9.6.6  OFC0: Offset Calibration Register 0 (address = 05h) [reset = depends on calibration results]
      7. 9.6.7  OFC1: Offset Calibration Register 1 (address = 06h) [reset = depends on calibration results]
      8. 9.6.8  OFC2: Offset Calibration Register 2 (address = 07h) [reset = depends on calibration results]
      9. 9.6.9  FSC0: Full-Scale Calibration Register 0 (address = 08h) [reset = depends on calibration results]
      10. 9.6.10 FSC1: Full-Scale Calibration Register 1 (address = 09h) [reset = depends on calibration results]
      11. 9.6.11 FSC2: Full-Scale Calibration Register 2 (address = 0Ah) [reset = depends on calibration results]
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Basic Connections
      2. 10.1.2 Digital Interface Connections
      3. 10.1.3 Analog Input Filtering
      4. 10.1.4 External Reference
      5. 10.1.5 Isolated (or Floating) Sensor Inputs
      6. 10.1.6 Unused Inputs and Outputs
      7. 10.1.7 Pseudo Code Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Detailed Design Procedure for ±10-V Input
          1. 10.2.2.1.1 Absolute Input Voltage Range
          2. 10.2.2.1.2 Differential Input Voltage Range
          3. 10.2.2.1.3 Level-Shifted Resistor Divider Sizing
          4. 10.2.2.1.4 Input Filtering
          5. 10.2.2.1.5 Register Settings for ±10-V Input
          6. 10.2.2.1.6 Voltage Input Design Variations
        2. 10.2.2.2 Detailed Design Procedure for 4-mA to 20-mA Input
          1. 10.2.2.2.1 PGA Gain Selection
          2. 10.2.2.2.2 Current-Sense Resistor Sizing
          3. 10.2.2.2.3 Register Settings for 4-mA to 20-mA Input
          4. 10.2.2.2.4 Current Input Design Variations
      3. 10.2.3 Application Curves
    3. 10.3 Dos and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

12 Layout

12.1 Layout Guidelines

Employ best design practices when laying out a printed circuit board (PCB) for both analog and digital components. Best design practice is to separate analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog multiplexers] from noise generating digital components [such as microcontrollers and switching regulators]. An example of good component placement is shown in Figure 73. Although Figure 73 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any high-resolution analog components.

ADS1257 ai_comp_plcmt_bas501.gif Figure 73. System Component Placement Example

The following outlines some basic recommendations for the layout of the ADS1257 to get the best possible performance of the ADC. A good design can be ruined with a bad circuit layout.

  • Separate analog and digital signals. Partition the board into analog and digital sections when the layout permits. Route digital lines away from analog lines to help prevent digital noise from coupling into analog signals.
  • Avoid splitting analog and digital ground planes. When possible, use a single solid ground plane for both analog and digital signals. A low impedance connection between AGND and DGND with minimal voltage difference between the ADS1257 analog and digital ground pins (AGND and DGND) is essential for optimum performance. If the system employs split digital and analog ground planes, connect the ground planes together as close to the device as possible.
  • Fill void areas on signal layers with ground fill.
  • Provide good ground return paths. Signal return currents follow the path of least impedance. If the ground plane is cut or has other traces that block the current from flowing adjacent to the signal trace, the current finds another path to return the source. If forced onto a longer path, the return current increases the possibility that the signal radiates or interferes with other sensitive circuitry.
  • Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass capacitors and the active device. For best results, place the bypass capacitors on the same layer and as close to the active device as possible.
  • Consider the resistance and inductance of the routing. Large resistance on the input traces can react with the input bias current and cause an added offset voltage. Reduce loop areas enclosed by the source signal and the return current in order to reduce input inductance and help prevent EMI pickup.
  • Route all differential signal traces as matched differential pairs. When possible, use adjacent analog inputs, such as AIN0, AIN1 and AIN2, AIN3, for differential measurements.
  • Analog inputs with differential connections must have a differential filtering capacitor placed across the inputs. Use high-quality differential capacitors, such as C0G (NPO) dielectric capacitors, that have stable properties and low-noise characteristics.

12.2 Layout Example

Figure 74 shows an example layout for the ADS1257 with a four layer PCB (only three layers are visible).

ADS1257 ai_pcb_layout_ex_bas656.gif Figure 74. Four-Layer PCB Layout Example

Analog and digital grounds share a ground plane. Do not place other traces are placed on the ground plane layer. Multiple parallel vias are used to reduce ground connection impedance and connect ground planes on multiple layers. Analog and digital signals are partitioned into separate areas on the PCB (as if a ground split was made) to reduce the potential for digital noise to couple into the analog signals. Where possible, ground plane fill is used on all layers.

Supply and reference signals are shown as traces routed on the top layer; however, these signals can also be provided to the ADS1257 through an internal layer. For best performance, the negative reference signal (REFN) must be routed back to the reference source with a trace and connected to ground near the reference source, to prevent ground plane currents from coupling into this signal. Route signal traces as differential pairs to minimize noise pick-up from adjacent traces.

Digital signals with fast rise and fall times are subject to ringing and overshoot if not properly terminated. Series resistors placed near the driving source terminate the transmission line of the PCB trace and suppress voltage ringing. When routing digital signals, give priority to CLKIN and SCLK signals. Keep clock traces as short as possible, routed directly above a ground plane, and routed with a minimum number of vias. GPIOs and control signal traces with slower edges and less frequent switching (such as D0, CS, SYNC/PWDN, and RESET) are not as sensitive to layout and can be made longer and use additional vias to make room for more critical digital signals (such as CLKIN, SCLK, DIN, and DOUT). Note that when multiple ADS1257s are used, the external clock signal can be routed to CLKIN on one device, and then serially connected from CLKOUT to CLKIN on the next device to simplify layout.