ZHCSSA6C september   2009  – june 2023 ADS1000-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog-to-Digital Converter
      2. 7.3.2 Clock Generator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Reset and Power Up
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
      2. 7.5.2 ADS1000-Q1 I2C Addresses
      3. 7.5.3 I2C General Call
      4. 7.5.4 I2C Data Rates
      5. 7.5.5 Output Code Calculation
    6. 7.6 Register Maps
      1. 7.6.1 Output Register
      2. 7.6.2 Configuration Register
      3. 7.6.3 Reading From the ADS1000-Q1
      4. 7.6.4 Writing to the ADS1000-Q1
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Connections
        1. 8.1.1.1 Connecting Multiple Devices
        2. 8.1.1.2 Using GPIO Ports For I2C
        3. 8.1.1.3 Single-Ended Inputs
    2. 8.2 Typical Applications
      1. 8.2.1 ADS1000-Q1 With Current-Shunt Monitor
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Part Selection
            1. 8.2.1.2.1.1 Gain Settings
            2. 8.2.1.2.1.2 Circuit Implementation
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Low-Side Current Measurement
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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7.6.2 Configuration Register

A user controls the ADS1000-Q1 operating mode and PGA settings through the 8-bit configuration register. The configuration register format is shown in Figure 7-2. The default setting is 80h.

Figure 7-2 Configuration Register
7 6 5 4 3 2 1 0
ST/BSY Reserved SC Reserved PGA[1:0]
Table 7-1 Configuration Register Field Description
Bit Field Type Reset Description
7 ST/BSY RW 1b

The meaning of the ST/BSY bit depends on whether the bit is being written to or read from. In single conversion mode, writing a 1b to the ST/BSY bit causes a conversion to start, and writing a 0b has no effect. In continuous conversion mode, the ADS1000-Q1 ignores the value written to ST/BSY.

When read in single conversion mode, ST/BSY indicates whether the A/D converter is busy taking a conversion. If ST/BSY is read as 1b, the A/D converter is busy, and a conversion is taking place; if 0b, no conversion is taking place, and the result of the last conversion is available in the output register. In continuous conversion mode, ST/BSY is always read as 1b.
6-5 Reserved R 00b Reserved. Always reads 00b.
4 SC RW 0b SC controls whether the ADS1000-Q1 is in continuous conversion or single conversion mode.

0b: Continuous conversion mode

1b: Single conversion mode
3-2 Reserved R 00b Reserved. Always reads 00b.
1-0 PGA[1:0] RW 00b PGA[1:0] bits control the ADS1000-Q1 gain setting.

00b: Gain = 1

01b: Gain = 2

10b: Gain = 4

11b: Gain = 8