ZHCSLJ1C July   2020  – December 2022 ADC3541 , ADC3542 , ADC3543

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3541
    8. 6.8  Electrical Characteristics - AC Specifications ADC3542
    9. 6.9  Electrical Characteristics - AC Specifications ADC3543
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics: ADC3541
    12. 6.12 Typical Characteristics: ADC3542
    13. 6.13 Typical Characteristics: ADC3543
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 Digital Filter Operation
        2. 8.3.4.2 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration Using the SPI Interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Sampling Clock
        3. 9.2.2.3 Voltage Reference
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-20211222-SS0I-HJKL-RVMG-75QZDQDP4JRX-low.pngFigure 5-1 RSB Package, 40-Pin WQFN
(Top View)
Table 5-1 Pin Descriptions
PINI/ODESCRIPTION
NAMENO.
INPUT/REFERENCE
AINM14INegative analog input
AINP13IPositive analog input
REFBUF4I1.2-V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND3IReference ground input, 0 V
VCM9OCommon-mode voltage output for the analog inputs, 0.95 V
VREF2IExternal voltage reference input, 1.6 V.
CLOCK
CLKM7INegative differential sampling clock input for the ADC
CLKP6IPositive differential sampling clock input for the ADC
CONFIGURATION
PDN/SYNC1IPower down, synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET10IHardware reset; active high. This pin has an internal 21 kΩ pull-down resistor.
SCLK40ISerial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO39ISerial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
SEN17ISerial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
DIGITAL INTERFACE

DCLK

26

O

CMOS output for data bit clock.

D038OSDR CMOS output used with 18 bit output (configured via output bit formatter). This becomes the LSB. When not used it can be left unconnected.
See Section 8.3.5.4 and Section 8.3.5.5 on how to change the output resolution and output bit mapping.
D137OSDR CMOS output used with 16 bit output (configured via output bit formatter). This becomes the LSB. When not used it can be left unconnected.
D236OSDR CMOS output for data bit D0 (14 bit LSB).
D3/

DCLKIN

35I/OSDR CMOS output for data bit D1. Used as DCLKIN for serial CMOS output modes.
D434OSDR CMOS output for data bit D2.
D533OSDR CMOS output for data bit D3.
D632OSDR CMOS output for data bit D4.
D730OSDR CMOS output for data bit D5.
D829OSDR CMOS output for data bit D6.
D928OSDR CMOS output for data bit D7.
D1027OSDR CMOS output for data bit D8.
D11/ Serial Lane 024OSDR CMOS output for data bit D9. DDR CMOS output for data bits D6/D13 (MSB). Lane 0 in serial CMOS output mode.
D12/

Serial Lane 1

23OSDR CMOS output for data bit D10. DDR CMOS output for data bits D5/D12. Lane 1 in serial CMOS output mode.
D1322OSDR CMOS output for data bit D11.

DDR CMOS output for data bits D4/D11.

D1421OSDR CMOS output for data bit D12.

DDR CMOS output for data bits D3/D10.

D1520OCMOS output for data bit D13 (MSB).

DDR CMOS output for data bits D2/D9.

D16/ FCLK19OSDR CMOS output used with 16 bit output (configured via output bit formatter). This becomes the MSB. When not used it can be left unconnected.

DDR CMOS output for data bits D1/D8. Frame clock output in serial CMOS output mode.

D17

18

O

SDR CMOS output used with 18 bit output (configured via output bit formatter). This becomes the MSB. When not used it can be left unconnected.

DDR CMOS output for data bits D0/D7 (LSB).

POWER SUPPLY
AVDD5,8,11,16IAnalog 1.8-V power supply
GND12,15IGround, 0 V
IOGND25IGround, 0 V for digital interface
IOVDD31I1.8-V power supply for digital interface
PowerPAD™----Connect to ground.