ZHCSLJ1C July   2020  – December 2022 ADC3541 , ADC3542 , ADC3543

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3541
    8. 6.8  Electrical Characteristics - AC Specifications ADC3542
    9. 6.9  Electrical Characteristics - AC Specifications ADC3543
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics: ADC3541
    12. 6.12 Typical Characteristics: ADC3542
    13. 6.13 Typical Characteristics: ADC3543
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 Digital Filter Operation
        2. 8.3.4.2 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration Using the SPI Interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Sampling Clock
        3. 9.2.2.3 Voltage Reference
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.6 Register Map

Table 8-15 Register Map Summary
REGISTER
ADDRESS		 REGISTER DATA
A[11:0] D7 D6 D5 D4 D3 D2 D1 D0
0x00 0 0 0 0 0 0 0 RESET
0x07 OP IF MAPPER 0 OP IF EN OP IF SEL
0x08 0 0 PDN CLKBUF PDN REFAMP 0 PDN A 1 PDN GLOBAL
0x0A CMOS OB DIS [7:0]
0x0B CMOS OB DIS [15:8]
0x0C CMOS OB DIS [23:16]
0x0D 0 0 MASK REFSYS A 0 MASK CLKBUF MASK REFAMP MASK BG DIS 0
0x0E SYNC PIN EN SPI SYNC SPI SYNC EN 0 REF CTRL REF SEL SE CLK EN
0x11 0 0 SE A 0 0 DLL PDN 0 AZ EN
0x13 0 0 0 0 0 0 0 E-FUSE LD
0x14 CUSTOM PAT [7:0]
0x15 CUSTOM PAT [15:8]
0x16 0 0 0 TEST PAT A CUSTOM PAT [17:16]
0x18 0 0 0 DCLKIN EN 0 0 0 0
0x19 FCLK SRC 0 0 FCLK DIV 0 0 FCLK EN 0
0x1B MAPPER EN 20B EN BIT MAPPER RES 0 0 0
0x1E 0 0 CMOS DCLK DEL 0 0 0 0
0x1F LOW DR EN DCLKIN EN 0 DCLK OB EN 2X DCLK 0 0 0
0x20 FCLK PAT [7:0]
0x21 FCLK PAT [15:8]
0x22 0 0 0 0 FCLK PAT [19:16]
0x24 0 0 0 0 0 DIG BYP DDC EN 0
0x25 0 DECIMATION REAL OUT 0 0 MIX PHASE
0x26 MIX GAIN A MIX RES A FS/4 MIX A 0 0 0 0
0x27 0 0 0 OP ORDER A Q-DEL A FS/4 MIX PH A 0 0
0x2A NCO A [7:0]
0x2B NCO A [15:8]
0x2C NCO A [23:16]
0x2D NCO A [31:24]
0x39..0x72 OUTPUT BIT MAPPER
0x8F 0 0 0 0 0 0 FORMAT A 0