ZHCSLJ1C July   2020  – December 2022 ADC3541 , ADC3542 , ADC3543

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3541
    8. 6.8  Electrical Characteristics - AC Specifications ADC3542
    9. 6.9  Electrical Characteristics - AC Specifications ADC3543
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics: ADC3541
    12. 6.12 Typical Characteristics: ADC3542
    13. 6.13 Typical Characteristics: ADC3543
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 Digital Filter Operation
        2. 8.3.4.2 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration Using the SPI Interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Sampling Clock
        3. 9.2.2.3 Voltage Reference
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.3.5.5 Output Bit Mapper

The output bit mapper allows to change the output bit order for any selected interface mode.

Figure 8-42 Output Bit Mapper

It is a two step process to change the output bit mapping and assemble the output data bus:

  1. In parallel interface mode, the maximum output resolution is 18-bit, in serial interface mode the maximum output resolution is 20-bit. Each output bit of either channel has a unique identifier bit as shown in the Table 8-10. The MSB starts with bit D19 – depending on output resolution chosen the LSB would be D6 (14-bit) to D0 (20-bit). The ‘previous sample’ is only needed in 2-w mode.
  2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap both a parallel and a serial output format.

Table 8-10 Unique identifier of each data bit
BitPrevious sample (2w only)Current sample
D19 (MSB)0x2D0x6D
D180x2C0x6C
D170x270x67
D160x260x66
D150x250x65
D140x240x64
D130x1F0x5F
D120x1E0x5E
D110x1D0x5D
D100x1C0x5C
D90x170x57
D80x160x56
D70x150x55
D60x140x54
D50x0F0x4F
D40x0E0x4E
D30x0D0x4D
D20x0C0x4C
D10x070x47
D0 (LSB)0x060x46

In parallel SDR mode, a data bit (with unique identifier) needs to be assigned to each output pin using the register addresses as shown in Figure 8-43. The example on the right shows the 14-bit output data bus remapped to reverse order to where the MSB starts on pin D2 instead of pin D15.

Figure 8-43 SDR output mapping (left) and example (right)

In parallel DDR mode, a data bit (with unique identifier) needs to be assigned to each output pin for both the rising and the falling edge of the DCLK using the register addresses as shown on the left of Figure 8-44. D9 and D10 are used for 16 and 18-bit output. The example on the right shows the 14-bit output data bus remapped to where the MSB starts on D17 instead of D11.

Figure 8-44 DDR output timing mapping (left) and example (right)

In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the serial output stream. There are a total of 40 addresses (0x39 to 0x60). When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample.

2-wire mode: in this mode both the current and the previous sample have to be used in the address space as shown in Figure 8-45 below. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused addresses between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.

Figure 8-45 2-wire output bit mapper

In the following example (Figure 8-46), the 16-bit 2-wire serial output is reordered to where pin D12 carries the 8 MSB and pin D11 carries 8 LSBs.

Figure 8-46 Example: 2-wire output mapping

1-wire mode: Only the ‘current’ sample needs to programmed in the address space.

Figure 8-47 1-wire output bit mapping