SNAS466G February   2009  – December 2016 ADC10D1000QML-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 6.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 6.7  Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics
    8. 6.8  Converter Electrical Characteristics: Channel-to-Channel Characteristics
    9. 6.9  Converter Electrical Characteristics: LVDS CLK Input Characteristics
    10. 6.10 Electrical Characteristics: AutoSync Feature
    11. 6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 6.12 Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode)
    13. 6.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 6.14 Timing Requirements: Serial Port Interface
    15. 6.15 Timing Requirements: Calibration
    16. 6.16 Quality Conformance Inspection
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Features
        1. 7.3.1.1 Input Control and Adjust
          1. 7.3.1.1.1 AC- and DC-Coupled Modes
          2. 7.3.1.1.2 Input Full-Scale Range Adjust
          3. 7.3.1.1.3 Input Offset Adjust
          4. 7.3.1.1.4 DES/Non-DES Mode
          5. 7.3.1.1.5 Sampling Clock Phase Adjust
          6. 7.3.1.1.6 LC Filter-On Input Clock
          7. 7.3.1.1.7 VCMO Adjust
        2. 7.3.1.2 Output Control and Adjust
          1. 7.3.1.2.1 DDR Clock Phase
          2. 7.3.1.2.2 LVDS Output Differential Voltage
          3. 7.3.1.2.3 LVDS Output Common-Mode Voltage
          4. 7.3.1.2.4 Output Formatting
          5. 7.3.1.2.5 Demux/Non-Demux Mode
          6. 7.3.1.2.6 Test Pattern Mode
        3. 7.3.1.3 Calibration Feature
          1. 7.3.1.3.1 Calibration Pins
          2. 7.3.1.3.2 How to Initiate a Calibration Event
          3. 7.3.1.3.3 On-Command Calibration
          4. 7.3.1.3.4 Calibration Adjust
          5. 7.3.1.3.5 Calibration and Power Down
          6. 7.3.1.3.6 Read/Write Calibration Settings
        4. 7.3.1.4 Power Down
      2. 7.3.2 Power-On Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Control Modes
        1. 7.4.1.1 Non-Extended Control Mode
          1. 7.4.1.1.1 Non-Demultiplexed Mode Pin (NDM)
          2. 7.4.1.1.2 Dual Data-Rate Phase Pin (DDRPh)
          3. 7.4.1.1.3 Calibration Pin (CAL)
          4. 7.4.1.1.4 Power-Down I-Channel Pin (PDI)
          5. 7.4.1.1.5 Power-Down Q-Channel Pin (PDQ)
          6. 7.4.1.1.6 Test Pattern Mode Pin (TPM)
          7. 7.4.1.1.7 Full-Scale Input Range Pin (FSR)
          8. 7.4.1.1.8 AC-DC-Coupled Mode Pin (VCMO)
          9. 7.4.1.1.9 LVDS Output Common-Mode Pin (VBG)
      2. 7.4.2 Extended Control Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
        1. 8.1.1.1 Acquiring the Input
        2. 8.1.1.2 Terminating Unused Analog Inputs
        3. 8.1.1.3 Reference Voltage and FSR
        4. 8.1.1.4 Out-of-Range Indication
        5. 8.1.1.5 AC-Coupled Input Signals
        6. 8.1.1.6 DC-Coupled Input Signals
        7. 8.1.1.7 Single-Ended Input Signals
      2. 8.1.2 Clock Inputs
        1. 8.1.2.1 CLK Coupling
        2. 8.1.2.2 CLK Frequency
        3. 8.1.2.3 CLK Level
        4. 8.1.2.4 CLK Duty Cycle
        5. 8.1.2.5 CLK Jitter
        6. 8.1.2.6 CLK Layout
      3. 8.1.3 The LVDS Outputs
        1. 8.1.3.1 Common-Mode and Differential Voltage
        2. 8.1.3.2 Output Data Rate
      4. 8.1.4 Synchronizing Multiple ADC10D1000S in a System
        1. 8.1.4.1 AutoSync Feature
        2. 8.1.4.2 DCLK Reset Feature
  9. 9 Power Supply Recommendations
    1. 9.1 Power Planes
      1. 9.1.1 Bypass Capacitors
        1. 9.1.1.1 Ground Plane
        2. 9.1.1.2 Power Supply Example
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Mounting Recommendation
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
    4. 10.4 Temperature Sensor Diode
    5. 10.5 Radiation Environments
      1. 10.5.1 Total Ionizing Dose
      2. 10.5.2 Single Event Latch-Up and Functional Interrupt
      3. 10.5.3 Single Event Upset
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Specification Definitions
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

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机械数据 (封装 | 引脚)
  • NAA|376
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Revision History

DATE RELEASED REVISION SECTION CHANGES
02/11/09 A Initial Release New Product Data Sheet Release
(ECN SENT FOR APPROVAL 02/05/09 - Edit #: 16)
03/18/09 B Connection Diagram, Table 3. Section 8.0 - DCLK_RST± diagram, Section 18.0, paragraph 18.4.2. Following Pin names corrected VA, GND and GNDDR. Section 8.0 - Update DCLK_RST± diagram, Section 18.0 - paragraph added to 18.4.2 and new figure. Revision A will be Archived.
4/20/09 C Features, Key Specifications, Table 10 Electricals. Moved reference to radiation to Features from Key Specifications. Table 10 Electricals: VOH typo limit move to Min., Added parameters VCMI_DRST, VID_DRST, RIN_DRST. Revision B will be Archived.
05/28/09 D Absolute Maximum Ratings and Operating Ratings, Electrical Section Table 12, Section 19 Reserved Addr: Fh Absolute Maximum Ratings added Voltage on VIN+, VIN-. Operating Ratings changed VIN+, VIN- Voltage Range. Range. Remove Note 10 reference from Table 12 tOSK, Correction to Reserved Addr: Fh. Revision C will be Archived.
09/11/09 E Electrical Section Table 12 Calibration (Tcal), 17.0 Section, 19.0 Section (top register 4h) Addr: 4h (0100b) POR state: DA7Fh Added Conditions to Tcal parameter, 17.0 Section New paragraph 17.4.3.4 and renumbered, Changed table 4h and title from Reserved to Calibration Adjust in 19.0 Section. Revision D will be Archived.
05/10/2010 F Ordering Information Table, Table 6, Table 10 Electrical Section. Sections 15.0, 17.0, 17.4.3, 19.0 Configuration Register 1 Bit 6 Added reference to MPR and CVAL NSPN. Table 6 section 1:2 Demux Non-DES Mode, Extended Control Mode, FM (14:0) = 7FFFh SNR Limit and 1:2 Demux Non-DES Mode, Non-Extended Control Mode, FSR = VA. Table 10 Digital Control Pins. Update Figure 11, Added New Figure 12 and 13, Renumbered previous Figure 12 and 13 to Figure 14 and 15 etc. Changed paragraph 17.4.3. Configuration Register 1– Bit 6 paragraph. Revision E will be Archived.
12/07/2016 G Added Device Information table, ESD Ratings table, Detailed Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section; updated values in the Thermal Information table to align with JEDEC standards; add pin VCMOS and information regarding usage throughout data sheet; update several pin names; removed maximum supply current values in Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode), leaving only power consumption specifications; conform other content to match format of similar data sheets in same device family; change "Panasonic part number ECJ-0EB1A104K" to "Presidio part number SR0402X7R104KENG5" in Power Supply; update Abs Max and ROC tables