SNAS466G February   2009  – December 2016 ADC10D1000QML-SP

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 6.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 6.7  Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics
    8. 6.8  Converter Electrical Characteristics: Channel-to-Channel Characteristics
    9. 6.9  Converter Electrical Characteristics: LVDS CLK Input Characteristics
    10. 6.10 Electrical Characteristics: AutoSync Feature
    11. 6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 6.12 Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode)
    13. 6.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 6.14 Timing Requirements: Serial Port Interface
    15. 6.15 Timing Requirements: Calibration
    16. 6.16 Quality Conformance Inspection
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Features
        1. 7.3.1.1 Input Control and Adjust
          1. 7.3.1.1.1 AC- and DC-Coupled Modes
          2. 7.3.1.1.2 Input Full-Scale Range Adjust
          3. 7.3.1.1.3 Input Offset Adjust
          4. 7.3.1.1.4 DES/Non-DES Mode
          5. 7.3.1.1.5 Sampling Clock Phase Adjust
          6. 7.3.1.1.6 LC Filter-On Input Clock
          7. 7.3.1.1.7 VCMO Adjust
        2. 7.3.1.2 Output Control and Adjust
          1. 7.3.1.2.1 DDR Clock Phase
          2. 7.3.1.2.2 LVDS Output Differential Voltage
          3. 7.3.1.2.3 LVDS Output Common-Mode Voltage
          4. 7.3.1.2.4 Output Formatting
          5. 7.3.1.2.5 Demux/Non-Demux Mode
          6. 7.3.1.2.6 Test Pattern Mode
        3. 7.3.1.3 Calibration Feature
          1. 7.3.1.3.1 Calibration Pins
          2. 7.3.1.3.2 How to Initiate a Calibration Event
          3. 7.3.1.3.3 On-Command Calibration
          4. 7.3.1.3.4 Calibration Adjust
          5. 7.3.1.3.5 Calibration and Power Down
          6. 7.3.1.3.6 Read/Write Calibration Settings
        4. 7.3.1.4 Power Down
      2. 7.3.2 Power-On Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Control Modes
        1. 7.4.1.1 Non-Extended Control Mode
          1. 7.4.1.1.1 Non-Demultiplexed Mode Pin (NDM)
          2. 7.4.1.1.2 Dual Data-Rate Phase Pin (DDRPh)
          3. 7.4.1.1.3 Calibration Pin (CAL)
          4. 7.4.1.1.4 Power-Down I-Channel Pin (PDI)
          5. 7.4.1.1.5 Power-Down Q-Channel Pin (PDQ)
          6. 7.4.1.1.6 Test Pattern Mode Pin (TPM)
          7. 7.4.1.1.7 Full-Scale Input Range Pin (FSR)
          8. 7.4.1.1.8 AC-DC-Coupled Mode Pin (VCMO)
          9. 7.4.1.1.9 LVDS Output Common-Mode Pin (VBG)
      2. 7.4.2 Extended Control Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
        1. 8.1.1.1 Acquiring the Input
        2. 8.1.1.2 Terminating Unused Analog Inputs
        3. 8.1.1.3 Reference Voltage and FSR
        4. 8.1.1.4 Out-of-Range Indication
        5. 8.1.1.5 AC-Coupled Input Signals
        6. 8.1.1.6 DC-Coupled Input Signals
        7. 8.1.1.7 Single-Ended Input Signals
      2. 8.1.2 Clock Inputs
        1. 8.1.2.1 CLK Coupling
        2. 8.1.2.2 CLK Frequency
        3. 8.1.2.3 CLK Level
        4. 8.1.2.4 CLK Duty Cycle
        5. 8.1.2.5 CLK Jitter
        6. 8.1.2.6 CLK Layout
      3. 8.1.3 The LVDS Outputs
        1. 8.1.3.1 Common-Mode and Differential Voltage
        2. 8.1.3.2 Output Data Rate
      4. 8.1.4 Synchronizing Multiple ADC10D1000S in a System
        1. 8.1.4.1 AutoSync Feature
        2. 8.1.4.2 DCLK Reset Feature
  9. Power Supply Recommendations
    1. 9.1 Power Planes
      1. 9.1.1 Bypass Capacitors
        1. 9.1.1.1 Ground Plane
        2. 9.1.1.2 Power Supply Example
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Mounting Recommendation
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
    4. 10.4 Temperature Sensor Diode
    5. 10.5 Radiation Environments
      1. 10.5.1 Total Ionizing Dose
      2. 10.5.2 Single Event Latch-Up and Functional Interrupt
      3. 10.5.3 Single Event Upset
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Specification Definitions
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

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订购信息

Detailed Description

Overview

The ADC10D1000 is a versatile analog-to-digital converter with an innovative architecture permitting very high-speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed here and in Application and Implementation. This section covers an overview and the control modes: extended control mode (ECM) and non extended control mode (non-ECM).

The ADC10D1000 uses a calibrated folding and interpolating architecture that achieves a high 9.0 effective number of bits (ENOB). The use of folding amplifiers greatly reduces the number of comparators and power consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input signal and further reducing power requirements. In addition to correcting other non-idealities, on-chip calibration reduces the INL bow often seen with folding architectures. The result is an extremely fast, high-performance, low-power converter. The calibration registers are radiation hard and are not upset by a heavy ion strike up to 120 MeV-cm2/mg.

The analog input signal (which is within the input voltage range of the converter) is digitized to ten bits at speeds of 200 MHz to 1300 MHz, typical. Differential input voltages below negative full-scale cause the output word to consist of all zeroes. Differential input voltages above positive full-scale cause the output word to consist of all ones. Either of these conditions at the I- or Q-input causes the out-of-range I-channel or Q-channel output (ORI or ORQ), respectively, to output a logic-high signal.

The device may be operated in one of two control modes: ECM or non-ECM. In non-ECM, the features of the device may be accessed via simple pin control. In ECM, an expanded feature set is available via the serial interface. Important new features include AutoSync for multi-chip synchronization, programmable 15-bit input full-scale range and independent programmable 12-bit plus sign offset adjustment.

Each channel has a selectable output demultiplexer, which feeds two LVDS buses. If the 1:2 demux mode is selected, the output data rate is reduced to half the input sample rate on each bus. When non-demux mode is selected, the output data rate on each channel is at the same rate as the input sample clock and only one 10-bit bus per channel is active.

Functional Block Diagram

ADC10D1000QML-SP 30071853.gif

Feature Description

Features

The ADC10D1000 offers many features to make the device convenient to use in a wide variety of applications. Table 1 is a summary of the features available, as well as details for the control mode chosen.

Table 1. Features and Modes

FEATURE NON-ECM CONTROL PIN ACTIVE IN ECM ECM DEFAULT ECM STATE
INPUT CONTROL AND ADJUST
Input full-scale adjust setting Selected via FSR
(pin Y3)
No Selected via the Configuration Register
(Addr: 3h and Bh)
mid FSR value
Input offset adjust setting Not available Not applicable Selected via the Configuration Register
(Addr: 2h and Ah)
Offset = 0 mV
LC filter on Clock Not available Not applicable Selected via the Configuration Register
(Addr: Dh)
LC filter off
Sampling clock phase adjust Not available Not applicable Selected via the Configuration Register
(Addr: Ch and Dh)
Phase adjust disable
DES/Non-DES mode selection Not available No Selected via DES bit (Addr: Ch and Dh Non-DES mode
VCMO adjust Not available Not applicable Selected via the Configuration Register (Addr: 1h) VCMO
OUTPUT CONTROL AND ADJUST
DDR clock phase selection Selected via DDRPh
(pin W4)
No Selected via DPS in the Configuration Register
(Addr: 0h; Bit: 14)
0° mode
LVDS differential output voltage amplitude selection Higher amplitude only Not applicable Selected via OVS in the Configuration Register
(Addr: 0h; Bit: 13)
Higher amplitude
LVDS common-mode output voltage amplitude selection Selected via VBG
(pin B1)
Yes Not available Higher amplitude
Output formatting selection Offset binary only Not applicable Selected via 2SC in the Configuration Register
(Addr: 0h; Bit: 4)
Offset binary
Test pattern mode at output Selected via TPM
(pin A4)
No Selected via TPM in the Configuration Register
(Addr: 0h; Bit: 12)
TPM not active
Demux/non-demux mode selection Selected via NDM
(pin A5)
Yes Not available N/A
AutoSync Not available Not applicable Selected via the Configuration Register (Addr: Eh) Master mode, RCOut1/2 disabled
DCLK RST Not available Not applicable Select via the Config Reg (Addr: Eh) DLCK reset disabled
CALIBRATION
On-command calibration event Selected via CAL
(pin D6)
Yes Selected via CAL in the Configuration Register
(Addr: 0h; Bit: 15)
N/A
(CAL = 0)
POWER-DOWN
Power down I channel Selected via PDI
(pin U3)
Yes Selected via PDI in the Configuration Register
(Addr: 0h; Bit: 11)
I channel operational
Power down Q channel Selected via PDQ
(pin V3)
Yes Selected via PDQ in theConfiguration Register
(Addr: 0h; Bit: 10)
Q channel operational

Input Control and Adjust

There are several features and configurations for the input of the ADC10D1000. This section covers input full-scale range adjust, input offset adjust, DES/non-DES modes, sampling clock phase adjust, and LC filter on the sampling clock.

AC- and DC-Coupled Modes

The analog inputs may be AC- or DC-coupled. See AC-DC-Coupled Mode Pin (VCMO) for information on how to select the desired mode; see DC-Coupled Input Signals and AC-Coupled Input Signals for applications information.

Input Full-Scale Range Adjust

The input full-scale range for the ADC10D1000 may be adjusted via non-ECM or ECM. In non-ECM, a control pin selects a higher or lower value; see Full-Scale Input Range Pin (FSR). In ECM, the input full-scale range may be selected with 15 bits of precision; see VIN_FSR in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics, for details. Note that the higher and lower full-scale input range settings in non-ECM do not correspond to the maximum and minimum full-scale input range settings in ECM. It is necessary to execute a manual calibration following any change of the input full-scale range. See Register Maps for information about the registers.

Input Offset Adjust

The input offset adjust for the ADC10D1000 may be adjusted with 12 bits of precision plus sign via ECM. See Register Maps for information about the registers.

DES/Non-DES Mode

The ADC10D1000 is available in dual-edge sampling (DES) or non-DES mode. The DES mode allows for the device Q-channel input to be sampled by the ADCs of both channels. One ADC samples the input on the rising edge of the input clock and the other ADC samples the same input on the falling edge of the input clock. A single input is thus sampled twice per input clock cycle, resulting in an overall sample rate of twice the input clock frequency, for example, 2 GSPS with a 1-GHz input clock. See for information on how to select the desired mode.

For the DES mode, only the Q channel may be used for the input. This may be selected in ECM by using the DES bit (Addr: 0h, Bit 7) to select the DES mode and the DESQ bit (Addr: 0h, Bit: 6) to select the Q channel as input.

In this mode, the outputs must be carefully interleaved in order to reconstruct the sampled signal. If the device is programmed into the 1:4 Demux DES mode, the data is effectively demultiplexed by 1:4. If the input clock is 1 GHz, the effective sampling rate is doubled to 2 GSPS, and each of the 4 output buses has an output rate of 500 MHz. All data is available in parallel. To properly reconstruct the sampled waveform, the four words of parallel data that are output with each DCLK must be correctly interleaved. The sampling order is as follows, from the earliest to the latest: DQd, DId, DQ, DI. See Figure 1. If the device is programmed into the non-demux DES mode, two bytes of parallel data are output with each edge of the DCLK in the following sampling order, from the earliest to the latest: DQ, DI. See Figure 4.

The performance of the ADC10D1000 in DES mode depends on how well the two channels are interleaved; that is, that the clock samples each channel with precisely a 50% duty cycle, each channel has the same offset (nominally code 511/512), and each channel has the same full-scale range. The ADC10D1000 also includes an automatic clock phase background adjustment in DES mode to automatically and continuously adjust the clock phase of the I and Q channels. This feature removes the need to adjust the clock phase setting manually and provides optimal performance in the DES mode. A difference exists in the typical offset between the I and Q channels, which can be removed via the offset adjust feature in ECM to optimize DES mode performance. To adjust the I- and Q-channel offset, measure a histogram of the digital data and adjust the offset via the control register until the histogram is centered at code 511/512. Similarly, the full-scale range of each channel may be adjusted for optimal performance.

Sampling Clock Phase Adjust

The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature is intended to help the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used, or simplify complex system functions such as beam steering for phase array antennas. A clock-jitter cleaner is available only when the CLK phase adjust feature is used. This adjustment delays all clocks, including the DCLKs and output data, and the user is strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in the system before relying on it.

LC Filter-On Input Clock

An LC bandpass filter is available on the ADC10D1000 sampling clock to clean jitter on the incoming clock. This feature is available when the CLK phase adjust is also used. This feature was designed to minimize the dynamic performance degradation resulting from additional clock jitter as much as possible. This feature is available in ECM via the LC filter (LCF) bits in the Control Register (Addr: Dh, Bits 7:0).

If the clock phase adjust feature is enabled, the sampling clock passes through additional gate delay, which adds jitter to the clock signal; the LCF helps to remove this additional jitter, so it is only available when the clock phase adjust feature is also enabled. To enable both features, use SA (Addr: Dh, Bit 8). The LCF bits are thermometer encoded and may be used to set a filter center frequency ranging from 0.8 GHz to 1.5 GHz; see Table 2.

Table 2. LC Filter Code vs FC

LCF(7:0) LCF(7:0) fC (GHz)
0 0000 0000b 1.5
1 0000 0001b 1.4
2 0000 0011b 1.3
3 0000 0111b 1.2
4 0000 1111b 1.1
5 0001 1111b 1
6 0011 1111b 0.92
7 0111 1111b 0.85
8 1111 1111b 0.8

The LC filter is a second-order bandpass filter, which has the following simulated bandwidth for a center frequency, fc at 1 GHz (see Table 3).

Table 3. LC Filter Bandwidth at 1 GHz

BANDWIDTH [dB] BANDWIDTH [MHz]
–3 ±135
–6 ±235
–9 ±360
–12 ±525

VCMO Adjust

The VCMO of the ADC10D1000QML is generated as a buffered version of the internal bandgap reference; see AC-DC-Coupled Mode Pin (VCMO). This pin provides an output voltage, which is the optimal common-mode voltage for the input signal and should be used to set the common-mode voltage of the driving buffer. However, in order to accommodate larger signals at the analog inputs, the VCMO may be adjusted to a lower value. From its typical default value, the VCMO may be lowered by approximately 200 mV via the VCA(2:0) bits of the Control Register (Addr: 1h; Bits: 7:5) in ECM. See Register Definitions for more information. Adjusting the VCMO away from its optimal value also degrades the dynamic performance; see VCMO in Recommended Operating Conditions.

Output Control and Adjust

There are several features and configurations for the output of the ADC10D1000 so that it may be used in many different applications. This section covers DDR clock phase, LVDS output differential and common-mode voltage, output formatting, Demux/Non-Demux Mode, and test pattern mode.

DDR Clock Phase

The ADC10D1000 output data is always delivered in double data rate (DDR). With DDR, the DCLK frequency is half the data rate and data is sent to the outputs on both edges of DCLK; see Figure 39. The DCLK-to-data phase relationship may be either 0° or 90°. For 0° mode, the data transitions on each edge of the DCLK. Any offset from this timing is tOSK; see Converter Electrical Characteristics: AC Electrical Characteristics for details. For 90° mode, the DCLK transitions in the middle of each data cell. Setup and hold times for this transition, tSU and tH, may also be found in Converter Electrical Characteristics: AC Electrical Characteristics. The DCLK-to-data phase relationship may be selected via the DDRPh Pin in Non-ECM (see Dual Data-Rate Phase Pin (DDRPh)) or the DPS bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM.

ADC10D1000QML-SP 30071894.gif Figure 39. DDR DCLK-to-Data Phase Relationship

LVDS Output Differential Voltage

The ADC10D1000 is available with a selectable higher or lower LVDS output differential voltage. This parameter is VOD and may be found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. The desired voltage may be selected via OVS Bit (Addr: 0h, Bit 13); see Register Maps for more information. In non-extended control mode only higher VOD is available.

LVDS Output Common-Mode Voltage

The ADC10D1000 is available with a selectable higher or lower LVDS output common-mode voltage. This parameter is VOS and may be found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. See LVDS Output Common-Mode Pin (VBG) for information on how to select the desired voltage.

Output Formatting

The formatting at the digital data outputs may be either offset binary or two's complement. The desired formatting is set via the 2SC bit of the Control Register (Addr: 0h; Bit: 4) in ECM; see Register Maps for more information.

Demux/Non-Demux Mode

The ADC10D1000 may be in one of two demultiplex modes: demux mode or non-demux mode (also sometimes referred to as 1:1 demux mode). In non-demux mode, the data from the input is simply output at the sampling rate at which it was sampled on one 10-bit bus. In demux mode, the data from the input is output at half the sampling rate, on twice the number of buses (see Functional Block Diagram). Demux or non-demux mode may only be selected by the NDM pin; see Non-Demultiplexed Mode Pin (NDM). In non-DES mode, the output data from each channel may be demultiplexed by a factor of 1:2 (1:2 demux non-DES mode). In DES mode, the output data from both channels interleaved may be demultiplexed (1:4 demux DES mode) or not demultiplexed (non-demux DES mode).

Test Pattern Mode

The ADC10D1000 can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In test-pattern mode, the ADC is disengaged, and a test pattern generator is connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES mode or non-DES mode. Each port is given a unique 10-bit word, alternating between 1's and 0's. When the device is programmed into the demux mode, the order of the test pattern is as described in Table 4.

Table 4. Test Pattern By Output Port In
1:2 Demux Mode

TIME Qd Id Q I ORQ ORI COMMENTS
T0 000h 001h 002h 004h 0b 0b Pattern sequence
n
T1 3FFh 3FEh 3FDh 3FBh 1b 1b
T2 000h 001h 002h 004h 0b 0b
T3 3FFh 3FEh 3FDh 3FBh 1b 1b
T4 000h 001h 002h 004h 0b 0b
T5 000h 001h 002h 004h 0b 0b Pattern sequence
n+1
T6 3FFh 3FEh 3FDh 3FBh 1b 1b
T7 000h 001h 002h 004h 0b 0b
T8 3FFh 3FEh 3FDh 3FBh 1b 1b
T9 000h 001h 002h 004h 0b 0b
T10 000h 001h 002h 004h 0b 0b Pattern sequence
n+2
T11 3FFh 3FEh 3FDh 3FBh 1b 1b
T12 000h 001h 002h 004h 0b 0b
T13 ... ... ... ... ... ...

When the device is programmed into the non-demux mode, the order of the test pattern is as described in Table 5.

Table 5. Test Pattern By Output Port In
Non-Demux Mode

TIME I Q ORI ORQ COMMENTS
T0 001h 000h 0b 0b Pattern
sequence
n
T1 001h 000h 0b 0b
T2 3FEh 3FFh 1b 1b
T3 3FEh 3FFh 1b 1b
T4 001h 000h 0b 0b
T5 3FEh 3FFh 1b 1b
T6 001h 000h 0b 0b
T7 3FEh 3FFh 1b 1b
T8 3FEh 3FFh 1b 1b
T9 3FEh 3FFh 1b 1b
T10 001h 000h 0b 0b Pattern
sequence
n+1
T11 001h 000h 0b 0b
T12 3FEh 3FFh 1b 1b
T13 3FEh 3FFh 1b 1b
T14 ... ... ... ...

Calibration Feature

The ADC10D1000 calibration must be run to achieve specified performance. The calibration procedure is exactly the same regardless of how it was initiated or when it is run. The DCLK outputs are present during all phases of the calibration process. All data and over-range output bits are held at logic low during calibration. Calibration must be performed in the planned mode of operation. Calibration trims the analog input differential termination resistor, the CLK input resistor, and sets internal bias currents which affects the linearity of the converter. This minimizes full-scale error, offset error, DNL and INL, resulting in maximizing the dynamic performance as measured by SNR, THD, SINAD (SNDR), and ENOB.

Calibration Pins

Table 6 is a summary of the pins used for calibration. See Pin Configuration and Functions for complete pin information and Figure 6 for the timing diagram.

Table 6. Calibration Pins

PIN NAME FUNCTION
D6 CAL
(calibration)
Initiate calibration event; see Calibration Pin (CAL)
B5 CalRun
(calibration running)
Indicates when calibration is running
C1/D2 Rtrim+, Rtrim–
(input termination trim resistor)
External resistor used to calibrate analog and CLK inputs
C3/D3 Rext+, Rext–
(external reference resistor)
External resistor used to calibrate internal linearity

How to Initiate a Calibration Event

The calibration event must be initiated by holding the CAL pin low for at least tCAL_L clock cycles, and then holding it high for at least another tCAL_H clock cycles, as defined in Timing Requirements: Calibration. The minimum tCAL_L and tCAL_H input clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired. The time taken by the calibration procedure is specified as tCAL. In ECM, either the CAL bit (Addr: 0h; Bit: 15) or the CAL pin may be used to initiate a calibration event.

On-Command Calibration

An on-command calibration must be run after power up and whenever the FSR is changed. TI recommends execution of an on-command calibration whenever the settings or conditions to the device are altered significantly, in order to obtain optimal parametric performance. Some examples include: changing the FSR via either ECM or non-ECM, power-cycling either channel, and switching into or out of DES mode. For best performance, it is also recommended that an on-command calibration be run 20 seconds or more after application of power and whenever the operating temperature changes significantly, relative to the specific system performance requirements.

Due to the nature of the calibration feature, TI recommends avoiding unnecessary activities on the device while the calibration is taking place. For example, do not read or write to the serial interface or use the DCLK reset feature while calibrating the ADC. Doing so impairs the performance of the device until it is re-calibrated correctly. Also, it is recommended to not apply a strong narrow-band signal to the analog inputs during calibration because this may impair the accuracy of the calibration; broad spectrum noise is acceptable.

Calibration Adjust

The calibration event itself may be adjusted, for sequence and mode. This feature can be used if a shorter calibration time than the default is required; see tCAL in Timing Requirements: Calibration. However, the performance of the device, when using a shorter calibration time than the default setting, is not ensured.

The calibration sequence may be adjusted via CSS (Addr: 4h, bit 14). The default setting of CSS = 1b executes both RIN and RIN_CLK calibration (using Rtrim) and internal linearity calibration (using Rext). Executing a calibration with CSS = 0b executes only the internal linearity calibration. The first time that calibration is executed, it must be with CSS = 1b to trim RIN and RIN_CLK. However, once the device is at its operating temperature, and RIN has been trimmed at least one time, it does not drift significantly. To save time in subsequent calibrations, trimming RIN and RIN_CLK may be skipped — that is, by setting CSS = 0b.

The mode may be changed, to save calibration execution time for the internal linearity calibration. See tCAL in Converter Electrical Characteristics: AC Electrical Characteristics. Adjusting the CMS(1:0) bits of the Calibration Adjust Register (Addr: 4h; Bits: 9:8) selects three different pre-defined calibration times. A longer of time calibrates each channel more closely to the ideal values, but choosing shorter times does not significantly impact the performance. The fourth setting, CMS(1:0) = 11b, is not available.

Calibration and Power Down

If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC10D1000 immediately powers down. The calibration cycle continues when either or both channels are powered back up, but the calibration is compromised due to the incomplete settling of bias currents directly after power up. Therefore, a new calibration must be executed upon powering the ADC10D1000 back up. In general, the ADC10D1000 must be re-calibrated when either or both channels are powered back up, or after one channel is powered down. For best results, power back up after the device has stabilized to its operating temperature.

Read/Write Calibration Settings

When the ADC performs a calibration, the calibration constants are stored in an array which is accessible via the Calibration Values Register (Addr: 5h). To save the time that it takes to execute a calibration, tCAL, or if re-using a previous calibration result, these values can be read from and written to the register at a later time. For example, if an application requires the same input impedance, RIN, this feature can be used to load a previously determined set of values. For the calibration values to be valid, the ADC must be operating under the same conditions, including temperature, at which the calibration values were originally read from the ADC.

To read calibration values from the SPI, do the following:

  1. Set ADC to desired operating conditions.
  2. Set SSC (Addr: 4h, Bit 7) to 1
  3. Read exactly 184 times the Calibration Values Register (Addr: 5h). The register values are R0, R1, R2... R183 where R0 is a dummy value. The contents of R <183:1> must be stored.
  4. Set SSC (Addr: 4h, Bit 7) to 0.
  5. Continue with normal operation.

To write calibration values to the SPI, do the following:

  1. Set ADC to operating conditions at which calibration values were previously read.
  2. Set SSC (Addr: 4h, Bit 7) to 1.
  3. Write exactly 183 times the Calibration Values Register (Addr: 5h). The registers should be written with stored register values R1, R2... R183.
  4. Make two additional dummy writes of 0000h.
  5. Set SSC (Addr: 4h, Bit 7) to 0.
  6. Continue with normal operation.

Power Down

On the ADC10D1000, the I and Q channels may be powered down individually. This may be accomplished via the control pins, PDI and PDQ, or via the PDI and PDQ bits of the Control Register (Addr: 0h; Bits: 11:10) in ECM. In ECM, the PDI and PDQ pins are logically OR'd with the Control Register setting. See Power-Down I-Channel Pin (PDI) and Power-Down Q-Channel Pin (PDQ) for more information.

Power-On Reset

The device power-on reset has been disabled to ensure single-effect functional interrupts do not occur during space operation. Therefore, the calibration routine at power-on is not reliable for the space version of the ADC10D1000. This means a manual calibration is always required after the device is power-on and is stable. Specifically, the device must either be in non-ECM or in ECM with the configuration registers reset or written to the correct values, and then a manual calibration must be run before the ADC can be used to digitize data correctly. See Calibration Feature for more information on calibration.

Device Functional Modes

Control Modes

The ADC10D1000 may be operated in one of two control modes: non-extended control mode (non-ECM) or extended control mode (ECM). In the simpler non-ECM (also sometimes referred to as pin-control mode), the user affects available configuration and control of the device through the control pins. The ECM provides additional configuration and control options through a serial interface and a set of 16 registers.

Non-Extended Control Mode

In non-ECM, the serial interface is not active and all available functions are controlled with various pin settings. Non-ECM is selected by setting ECE (pin B3) to logic high. Seven dedicated control pins provide a wide range of control for the ADC10D1000 and facilitate its operation. These control pins provide demux mode selection, DDR phase selection, calibration event initiation, power-down I channel, power-down Q channel, test-pattern mode selection, and full-scale input range selection. In addition to this, a one dual-purpose control pin provides for LVDS output common-mode voltage selection. See Table 7 for a summary.

Table 7. Non-ECM Pin Summary

PIN NAME LOGIC LOW LOGIC HIGH FLOATING
NDM demux mode non-demux mode Not allowed
DDRPh 0° mode 90° mode Not allowed
CAL See Calibration Pin (CAL) Not allowed
PDI I channel active Power-down
I channel
Not allowed
PDQ Q channel active Power-down
Q channel
Not allowed
TPM Non-test pattern mode Test pattern mode Not allowed
FSR Lower FS input range Higher FS input range Not allowed
DUAL-PURPOSE CONTROL PINS
VCMO AC-coupled operation Not allowed DC-coupled operation
VBG Not allowed Higher LVDS common-mode voltage Lower LVDS common-mode voltage

Non-Demultiplexed Mode Pin (NDM)

The non-demultiplexed mode (NDM) pin selects whether the ADC10D1000 is in demux mode (logic-low) or non-demux mode (logic-high). In Non-demux mode, the data from the input is produced at the data-rate at a single 10-bit output bus. In demux mode, the data from the input is produced at half the data-rate at twice the number of output buses. For non-des mode, each I or Q channel produces its data on one or two buses for non-demux mode or demux mode, respectively. For DES mode, the Q channel produces its data on two or four buses for non-demux mode or demux mode, respectively.

This feature is pin-controlled only and remains active during both non-ECM and ECM. See Table 7 for more information.

Dual Data-Rate Phase Pin (DDRPh)

The dual data-rate-phase (DDRPh) pin selects whether the ADC10D1000 is in 0° mode (logic-low) or 90° mode (logic-high). In dual data rate (DDR) mode, the data may transition either with the DCLK transition (0° mode) or halfway between DCLK transitions (90° mode). The data is always in DDR mode on the ADC10D1000. The DDRPh pin selects 0° mode or 90° mode for both the I-channel DI- and DId-to-DCLKI phase relationship and for the Q-channel DQ- and DQd-to-DCLKQ phase relationship.

To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See Table 11 for more information.

Calibration Pin (CAL)

The calibration pin (CAL) must be used to initiate an on-command calibration event. The effect of calibration is to maximize the dynamic performance. To initiate an on-command calibration via the CAL pin, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles. Hold the CAL pin high when not in use to ensure no undesired calibrating in space environment. In ECM mode this pin remains active and is logically OR'd with the CAL bit.

To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Calibration Feature for more information.

Power-Down I-Channel Pin (PDI)

The power-down I-channel (PDI) pin selects whether the I channel is powered down (logic-high) or active (logic-low). The digital data output pins (both positive and negative) are put into a high impedance state when the I channel is powered down. Upon return to the active state, the pipeline contains meaningless information and must be flushed. The supply currents (typicals and limits) are available for the I channel powered down or active and may be found in Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode). It is recommended that the user thoroughly understand how the PDI feature functions in relationship with the Calibration feature and control them appropriately for their application.

This pin remains active in ECM. In ECM, either this pin or the PDI bit (Addr: 0h; Bit: 11) in the Control Register may be used to power down the I channel. See Power Down for more information.

Power-Down Q-Channel Pin (PDQ)

The power-down Q-channel (PDQ) pin selects whether the Q- channel is powered down (logic-high) or active (logic-low). This pin functions similarly to the PDI pin, except that it applies to the Q channel. The PDI and PDQ pins function independently of each other to control whether each I channel or Q channel is powered down or active.

This pin remains active in ECM. In ECM, either this pin or the PDQ bit (Addr: 0h; Bit: 10) in the Control Register may be used to power-down the I channel. See Power Down for more information.

Test Pattern Mode Pin (TPM)

The test-pattern mode (TPM) pin selects whether the output of the ADC10D1000 is a test pattern (logic-high) or the converted input (logic-low). The ADC10D1000 can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In TPM, the ADC is disengaged, and a test pattern generator is connected to the outputs, including ORI and ORQ. See Test Pattern Mode for more information.

Full-Scale Input Range Pin (FSR)

The full-scale input range (FSR) pin selects whether the full-scale input range for both the I channel and Q channel is higher (logic-high) or lower (logic-low). The input full-scale range is specified as VIN_FSR in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics. In non-ECM, the full-scale input range for each I channel and Q channel may not be set independently, but it is possible to do so in ECM. The device must be calibrated following a change in FSR to obtain optimal performance.

To use this feature in ECM, use the Configuration Register (Addr: 3h and Bh). See Input Control and Adjust for more information.

AC-DC-Coupled Mode Pin (VCMO)

The VCMO pin serves a dual purpose. When functioning as an output, it provides the optimal common-mode voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is AC-coupled (logic-low) or DC-coupled (floating). This pin is always active, in both ECM and non-ECM.

LVDS Output Common-Mode Pin (VBG)

The VBG pin serves a dual purpose and may either provide the bandgap output voltage or select whether the LVDS output common-mode voltage is higher (logic-high) or lower (floating). The LVDS output common-mode voltage is specified as VOS and may be found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. This pin is always active, in both ECM and Non-ECM. See Output Control and Adjust for more information.

Extended Control Mode

In extended control mode (ECM), all available functions are controlled via the serial interface. In addition to this, several of the control pins remain active. See Table 1 for details. ECM is selected by setting ECE (pin B3) to logic low.

The space version of the ADC10D1000 does not include a power-on reset. Therefore, when powered up in ECM, the registers are in an unknown, random state. There are two ways to set the ECM registers: toggling the ECE pin or writing to the registers. If the device is programmed into non-ECM (by setting ECE logic high), the registers are programmed to their default values. Thus, if the ECE pin is set to logic high, then set to logic low (ECM), the device will be in ECM, and the registers will have their default values. The second method is to simply explicitly write the default (or otherwise desired) values to the register in ECM; TI recommends the second method.

Programming

Four pins on the ADC10D1000 control the serial interface: SCS, SCLK, SDI, and SDO. Serial Interface covers the serial interface. Also see Register Maps.

Serial Interface

The ADC10D1000 offers a serial interface that allows access to the sixteen control registers within the device. The serial interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible with SPI-type interfaces that are used on many microcontrollers and DSP controllers. Each serial interface access cycle is exactly 24 bits long. A register-read or register-write can be accomplished in one cycle. The signals are defined in such a way that the user can opt to simply join SDI and SDO signals in their system to accomplish a single, bidirectional SDI/O signal. A summary of the pins for this interface may be found in Table 8. See Figure 7 for the timing diagram and Converter Electrical Characteristics: AC Electrical Characteristics for timing specification details. Control register contents are retained when the device is put into power-down mode.

Table 8. Serial Interface Pins

PIN NAME
C4 SCS (serial chip select)
C5 SCLK (serial clock)
B4 SDI (serial data in)
A3 SDO (serial data out)

SCS: Each assertion (logic-low) of this signal starts a new register access; that is, the SDI command field must be ready. The user is required to de-assert this signal after the 24th clock. If the SCS is de-asserted before the 24th clock, no data read/write occurs. If the SCS is asserted longer than 24 clocks, data write occurs normally through the SDI input upon the 24th clock, and the SDO output holds the D0 bit until SCS is de-asserted. Setup and hold times, tSCS and tHCS, with respect to the SCLK must be observed.

SCLK: This signal is used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. The user may disable the clock and hold it in the low-state. There is no minimum frequency requirement for SCLK; see fSCLK in Timing Requirements: Serial Port Interface for more details.

SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field and a data field. When in read mode, the data field is high impedance in case the bidirectional SDI/O option is used. Setup and hold times, tSH and tSSU, with respect to the SCLK must be observed.

SDO: This output is normally tri-stated and is driven only when SCS is asserted, the first 8 bits of command data have been received and it is a READ operation. The data is shifted out, MSB first, starting with the 8th clock's falling edge. At the end of the access, when SCS is de-asserted, this output is tri-stated once again. If an invalid address is accessed, the data sourced consists of all zeroes. Setup and hold times, tSH and tSSU, with respect to the SCLK must be observed. If it is a READ operation, there is a bus turnaround time, tBSU, from when the last bit of the command field was read in until when the first bit of the data field is written out.

Table 9 shows the Serial Interface bit definitions.

Table 9. Command and Data Field Definitions

BIT NO. NAMES COMMENTS
1 Read/Write (R/W) 1b indicates a read operation
0b indicates a write operation
2-3 Reserved Bits must be set to 10b
4-7 A<3:0> 16 registers may be addressed. The order is MSB first
8 X This is a "don't care" bit
9-24 D<15:0> Data written to or read from addressed register
ADC10D1000QML-SP 30071813.gif Figure 40. Serial Interface Timing (Zoom Start)***

***SCS transition from High to Low must occur tHCS after the falling edge of SCLK, and tSCS before the rising edge of SCLK.

ADC10D1000QML-SP 30071814.gif Figure 41. Serial Interface Timing (Zoom End)****

****SCS transition from Low to High must occur tHCS after the 24th SCLK cycle during a low cycle.

The serial data protocol is shown for a read and write operation in Figure 42 and Figure 43, respectively.

ADC10D1000QML-SP 30071892.gif Figure 42. Serial Data Protocol - Read Operation
ADC10D1000QML-SP 30071893.gif Figure 43. Serial Data Protocol - Write Operation

Register Maps

Register Definitions

Eight read/write registers provide several control and configuration options in the extended control mode. These registers have no effect when the device is in the non-extended control mode. The ADC10D1000 does not have a power-on reset. The user can write the registers with the desired values, or in extended control mode set ECEb Logic high setting resisters to the default values.

Table 10. Register Addresses

A3 A2 A1 A0 Hex REGISTER ADDRESSED
0 0 0 0 0h Configuration Register 1
0 0 0 1 1h VCMO Adjust
0 0 1 0 2h I-channel Offset
0 0 1 1 3h I-channel FSR
0 1 0 0 4h Res
0 1 0 1 5h Res
0 1 1 0 6h Res
0 1 1 1 7h Res
1 0 0 0 8h Res
1 0 0 1 9h Res
1 0 1 0 Ah Q-Channel Offset
1 0 1 1 Bh Q-Channel FSR
1 1 0 0 Ch Aperture Delay Coarse Adjust
1 1 0 1 Dh Aperture Delay Fine Adjust and LC Filter Adjust
1 1 1 0 Eh AutoSync
1 1 1 1 Fh Res

Table 11. Configuration Register 1

Addr: 0h (0000b) Default Values: 2000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CAL DPS OVS TPM PDI PDQ Res LFS DES DESQ Res 2SC Res
DV 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration cycle is initiated. This bit is not reset automatically upon completion of the cal cycle. Therefore, the user must reset this bit to 0b and then set it to 1b again to initiate another calibration event. This bit is logically OR'd with the CAL pin; both bit and pin must be set to 0b before either is used to execute a calibration.
Bit 14 DPS: DDR phase select. Set this bit to 0b to select the 0° Mode DDR Data-to-DCLK phase relationship and to 1b to select the 90° mode. This bit has no effect when the device is in Non-Demux Mode.
Bit 13 OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, RCOut1, RCOut2 and DCLK. 0b selects the lower level and 1b selects the higher level. See VOD in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics for details.
Bit 12 TPM: Test Pattern Mode. When this bit is set to 1b, the device continually outputs a fixed digital pattern at the digital data and OR outputs. When set to 0b, the device continually outputs the converted signal, which was present at the analog inputs. See Test Pattern Mode for details about the TPM pattern.
Bit 11 PDI: Power-down I channel. When this bit is set to 0b, the I channel is fully operational, but when it is set to 1b, the I channel is powered down. The I channel may be powered down via this bit or the PDI pin, which is active, even in ECM.
Bit 10 PDQ: Power-down Q channel. When this bit is set to 0b, the Q channel is fully operational, but when it is set to 1b, the Q channel is powered down. The Q channel may be powered-down via this bit or the PDQ pin, which is active, even in ECM.
Bits 9 Reserved. Must be set to 0b.
Bits 8 LFS: Low Frequency Select. If the sampling Clock (CLK) is at or below 300 MHz, set this bit to 1b.
Bit 7 DES: Dual-Edge-Sampling Mode Select. When this bit is set to 0b, the device operates in the non-DES mode; when it is set to 1b, the device operates in the DES mode. See DES/Non-DES Mode for more information about DES/non-DES mode.
Bit 6 DESQ: DES Q-channel select. When the device is in DES mode; always set this bit to 1b selecting the Q channel.
Bit 5 Reserved. Must be set to 0b.
Bit 4 2SC: Two's Complement Output. For the default setting of 0b, the data is output in offset binary format; when set to 1b, the data is output in two's complement format.
Bits 3:0 Reserved. Must be set to 0b.

Table 12. VCMO Adjust

Addr: 1h (0001b) Default values: 2A00h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved VCA(2:0) Reserved
POR 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0
Bits 15:8 Reserved. Must be set as shown.
Bits 7:5 VCA(2:0): VCMO Adjust. Adjusting from the default VCA(2:0) = 0d to VCA(2:0) = 7d decreases VCMO from its typical value (see VCMO in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics) to 1.05 V by increments of ~28.6 mV.
CODE VCMO
000 (default) VCMO
100 VCMO– 114 mV
111 VCMO– 200 mV
Bits 4:0 Reserved. Must be set as shown.

Table 13. I-Channel Offset Adjust

Addr: 2h (0010b) Default Values: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved OS OM(11:0)
DV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15:13 Reserved. Must be set to 0b.
Bit 12 OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by bits 11:0 to the ADC output. Setting this bit to 1b incurs a negative offset of the set magnitude.
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 μV. Monotonicity is ensured by design only for the 9 MSBs.
CODE OFFSET [mV]
0000 0000 0000 (default) 0
1000 0000 0000 22.5
1111 1111 1111 45

Table 14. I-Channel Full Scale Range Adjust

Addr: 3h (0011b) Default Values: 4000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res. FM(14:0)
DV 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 Reserved. Must be set to 0b.
Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from 630 mV (0d) to 980 mV (32767d) with the default setting at 820 mV (162384d). Monotonicity is ensured by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR values is available in EC; that is, FSR values above 820 mV. See Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics for characterization details.
CODE FSR [mV]
000 0000 0000 0000 630
100 0000 0000 0000 (default) 820
111 1111 1111 1111 980

Table 15. Calibration Adjust

Addr: 4h (0100b) Default Values: DA7Fh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res CSS Reserved CMS Reserved
DV 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 1
Bit 15 Reserved. Must be set to 1b.
Bit 14 CSS: calibration sequence select. The default 1b selects the following calibration sequence: reset all previously calibrated elements to nominal values, do RIN calibration, do internal linearity calibration. Setting CSS = 0b selects the following calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal linearity calibration. The calibration must be completed at least one time with CSS = 1b to calibrate RIN. Subsequent calibrations may be run with CSS = 0b (skip RIN calibration) or 1b (full RIN and internal linearity calibration).
Bits 13:10 Reserved. Must be set as shown.
Bits 9:8 CMS(1:0): Calibration Mode Select. These bits affect the length of time taken to calibrate the internal linearity. CMS(1:0) = 11b is not available. See tCAL in Converter Electrical Characteristics: AC Electrical Characteristics.
Bits 7:0 Reserved. Must be set as shown.

Table 16. Reserved

Addr: 5h (0101b) Default Values: XXXXh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved
DV X X X X X X X X X X X X X X X X
Bits 15:0 Reserved. Do not write.

Table 17. Reserved

Addr: 6h (0110b) Default Values: 1C70h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved
DV 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0
Bits 15:0 Reserved. Must be set as shown.

Table 18. Reserved

Addr: 7h (0111b) Default Values: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved
DV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15:0 Reserved. Must be set as shown.

Table 19. Reserved

Addr: 8h (1000b) Default Values: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved
DV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15:0 Reserved. Must be set as shown.

Table 20. Reserved

Addr: 9h (1001b) Default Values: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved
DV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15:0 Reserved. Must be set as shown.

Table 21. Q-Channel Offset Adjust

Addr: Ah (1010b) Default Values: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved OS OM(11:0)
DV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15:13 Reserved. Must be set to 0b.
Bit 12 OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bit to 1b incurs a negative offset of the set magnitude.
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of -11 μV. Monotonicity is ensured by design only for the 9MSBs.
CODE OFFSET [mV]
0000 0000 0000 (default) 0
1000 0000 0000 22.5
1111 1111 1111 45

Table 22. Q-Channel Full-Scale Range Adjust

Addr: Bh (1011b) Default Values: 4000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res FM(14:0)
DV 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 Reserved. Must be set to 0b.
Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from 630 mV (0d) to 980 mV (32767d) with the default setting at 820 mV (16384d). Monotonicity is ensured by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR values is available in ECM; that is, FSR values above 820 mV. See Converter Electrical Characteristics: Analog Input/Output and Reference Characteristicsfor characterization details.
CODE FSR [mV]
000 0000 0000 0000 630
100 0000 0000 0000 (default) 820
111 1111 1111 1111 980

Table 23. Aperture Delay Coarse Adjust

Addr: Ch (1100b) Default Values: 0004h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CAM(11:0) STA DCC Reserved
DV 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bits 15:4 CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to the input CLK signal. The range is 0 ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for CAM(11:0) = 2431d (±95 ps due to PVT variation) in steps of ~340 fs. For code CAM(11:0) = 2432d and above, the delay saturates and the maximum delay applies. Additional, finer delay steps are available in register Dh. Either STA (Bit 3) or SA (Addr: Dh, Bit 8) must be selected to enable this function.
Bit 3 STA: Select tAD Adjust. Set this bit to 1b to enable the tAD adjust feature. When using this feature, make sure that SA (Addr: Dh, Bit 8) is set to 0b.
Bit 2 DCC: Duty Cycle Correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the chip. This feature is enabled by default.
Bits 1:0 Reserved. Must be set to 0b.

Table 24. Aperture Delay Fine Adjust and LC Filter Adjust

Addr: Dh (1101b) Default Values: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FAM(5:0) Res SA LCF(7:0)
DV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will be applied to the input CLK when the Clock Phase Adjust feature is enabled via STA (Addr: Ch, Bit 3) or SA (Addr: Dh, Bit 8). The range is straight binary from 0 ps delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) = 63d (±300 fs due to PVT variation) in steps of ~36 fs.
Bit 9 Reserved. Must be set to 0b.
Bit 8 SA: Select tAD and LC filter adjust. Set this bit to 1b to enable the tAD and LC filter adjust features. Using this bit is the same as enabling STA (Addr: Ch, Bit3), but also enables the LC filter to clean the clock jitter.
Bits 7:0 LCF(7:0): LC tank select frequency. Use these bits to select the center frequency of the LC filter on the Clock inputs. The range is from 0.8 GHz (255d) to 1.5 GHz (0d). Note that the tuning range is not binary encoded, and the eight bits are thermometer encoded; that is, the mid value of 1.1 GHz tuning is achieved with LCF(7:0) = 0000 1111b.

Table 25. AutoSync

Addr: Eh (1110b) Default Values: 0003h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DRC(9:0) Res. SP(1:0) ES DOC DR
DV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bits 15:6 DRC(9:0): Delay Reference Clock (9:0). These bits may be used to increase the delay on the input reference clock when synchronizing multiple ADCs. The minimum delay is 0s (0d) to 1000 ps (639d). The delay remains the maximum of 1000 ps for any codes above or equal to 639d.
Bit 5 Reserved. Must be set to 0b.
Bits 4:3 SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond to the following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
Bit 2 ES: Enable Slave. Set this bit to 1b to enable the slave mode of operation. In this mode, the internal divided clocks are synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK+ or RCLK-. If this bit is set to 0b, then the device is in master mode.
Bit 1 DOC: Disable Output Reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The default setting of 1b disables these output drivers. This bit functions as described, regardless of whether the device is operating in master or slave mode, as determined by ES (Bit 2).
Bit 0 DR: Disable Reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable DCLK_RST functionality.

Table 26. Reserved

Addr: Fh (1111b) Default Values: XXXXh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved
DV X X X X X X X X X X X X X X X X
Bits 15:0 Reserved. Do not write.