ZHCSDH0C December   2014  – January 2018 LP3907-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用电路
  4. 4 修订历史记录
  5. 5 器件比较 台式机
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions (Bucks)
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Low Dropout Regulators, LDO1 And LDO2
    7. 7.7  Buck Converters SW1, SW2
    8. 7.8  I/O Electrical Characteristics
    9. 7.9  Power-On Reset (POR) Threshold/Function
    10. 7.10 I2C Interface Timing Requirements
    11. 7.11 Typical Characteristics — LDO
    12. 7.12 Typical Characteristics — Bucks
    13. 7.13 Typical Characteristics — Buck1
    14. 7.14 Typical Characteristics — Buck2
    15. 7.15 Typical Characteristics — Bucks
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC-DC Converters
        1. 8.3.1.1 Linear Low Dropout Regulators (LDOs)
        2. 8.3.1.2 No-Load Stability
        3. 8.3.1.3 LDO and LDO2 Control Registers
      2. 8.3.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters
        1. 8.3.2.1  Functional Description
        2. 8.3.2.2  Circuit Operation Description
        3. 8.3.2.3  PWM Operation
        4. 8.3.2.4  Internal Synchronous Rectification
        5. 8.3.2.5  Current Limiting
        6. 8.3.2.6  PFM Operation
        7. 8.3.2.7  SW1, SW2 Operation
        8. 8.3.2.8  SW1, SW2 Control Registers
        9. 8.3.2.9  Soft Start
        10. 8.3.2.10 Low Dropout Operation
        11. 8.3.2.11 Flexible Power Sequencing of Multiple Power Supplies
        12. 8.3.2.12 Power-Up Sequencing Using the EN_T Function
      3. 8.3.3 Flexible Power-On Reset (Power Good with Delay)
      4. 8.3.4 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Interface
        1. 8.5.1.1 I2C Signals
        2. 8.5.1.2 I2C Data Validity
        3. 8.5.1.3 I2C Start and Stop Conditions
        4. 8.5.1.4 Transferring Data
      2. 8.5.2 Factory Programmable Options
    6. 8.6 Register Maps
      1. 8.6.1 LP3907-Q1 Control Registers
        1. 8.6.1.1  Interrupt Status Register (ISRA) 0x02
        2. 8.6.1.2  Control 1 Register (SCR1) 0x07
        3. 8.6.1.3  EN_DLY Preset Delay Sequence After EN_T Assertion
        4. 8.6.1.4  Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10
        5. 8.6.1.5  Buck and LDO Status Register (BKLDOSR) – 0x11
        6. 8.6.1.6  Buck Voltage Change Control Register 1 (VCCR) – 0x20
        7. 8.6.1.7  Buck1 Target Voltage 1 Register (B1TV1) – 0x23
        8. 8.6.1.8  Buck1 Target Voltage 2 Register (B1TV2) – 0x24
        9. 8.6.1.9  Buck1 Ramp Control Register (B1RC) - 0x25
        10. 8.6.1.10 Buck2 Target Voltage 1 Register (B2TV1) – 0x29
        11. 8.6.1.11 Buck2 Target Voltage 2 Register (B2TV2) – 0x2A
        12. 8.6.1.12 Buck2 Ramp Control Register (B2RC) - 0x2B
        13. 8.6.1.13 Buck Function Register (BFCR) – 0x38
        14. 8.6.1.14 LDO1 Control Register (LDO1VCR) – 0x39
        15. 8.6.1.15 LDO2 Control Register (LDO2VCR) – 0x3A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Component Selection
          1. 9.2.2.1.1 Inductors for SW1 And SW2
            1. 9.2.2.1.1.1 Method 1:
            2. 9.2.2.1.1.2 Method 2:
          2. 9.2.2.1.2 External Capacitors
        2. 9.2.2.2 LDO Capacitor Selection
          1. 9.2.2.2.1 Input Capacitor
          2. 9.2.2.2.2 Output Capacitor
          3. 9.2.2.2.3 Capacitor Characteristics
          4. 9.2.2.2.4 Input Capacitor Selection for SW1 And SW2
          5. 9.2.2.2.5 Output Capacitor Selection for SW1, SW2
          6. 9.2.2.2.6 I2C Pullup Resistor
        3. 9.2.2.3 Operation Without I2C Interface
          1. 9.2.2.3.1 High VIN High-Load Operation
          2. 9.2.2.3.2 Junction Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Analog Power Signal Routing
  11. 11Layout
    1. 11.1 DSBGA Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations of WQFN Package
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 商标
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

8.3.2.12 Power-Up Sequencing Using the EN_T Function

EN_T assertion causes the LP3907-Q1 to emerge from Standby mode to Full Operation mode at a preset timing sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are 500 KΩ internally pulled down, which causes the part to stay OFF until enabled. If the user wishes to use the preset timing sequence to power on the regulators, transition the EN_T pin from Low to High. Otherwise, simply tie the enables of each specific regulator HIGH to turn on automatically.

EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched, and the default is set at 1 ms. As shown in Figure 32 and Figure 33, a rising EN_T edge starts a power-on sequence, while a falling EN_T edge starts a shutdown sequence. If EN_T is high, toggling the external enables of the regulators has no effect on the chip.

The regulators can also be programmed through I2C to turn on and off. By default, I2C enables for the regulators turned ON.

The regulators are on following the pattern below:

Regulators on = (I2C enable) AND (External pin enable OR EN_T high).

NOTE

The EN_T power-up sequencing may also be employed immediately after VIN is applied to the device. However, VIN must be stable for approximately 8 ms minimum before EN_T be asserted high to ensure internal bias, reference, and the Flexible POR timing are stabilized. This initial EN_T delay is necessary only upon first time device power on for power sequencing function to operate properly. If the device is powered, the EN_T logic must be stable for 12 ms minimum before switching state.

LP3907-Q1 30017809.gifFigure 32. Power Rail Enable Logic
LP3907-Q1 30017810.gifFigure 33. LP3907-Q1 Default Power-Up Sequence

Table 5. Power-On Timing Specification

DESCRIPTION MIN NOM TYP UNIT
t1 Programmable delay from EN_T assertion to VCC_Buck1 On 1.5 ms
t2 Programmable delay from EN_T assertion to VCC_Buck2 On 2 ms
t3 Programmable delay from EN_T assertion to VCC_LDO1 On 3 ms
t4 Programmable delay from EN_T assertion to VCC_LDO2 On 6 ms
LP3907-Q1 30017811.gifFigure 34. LP3907-Q1 Default Power-Off Sequence

Table 6. Power-Off Timing Specification

DESCRIPTION MIN NOM MAX UNIT
t1 Programmable delay from EN_T deassertion to VCC_Buck1 Off 1.5 ms
t2 Programmable delay from EN_T deassertion to VCC_Buck2 Off 2 ms
t3 Programmable delay from EN_T deassertion to VCC_LDO1 Off 3 ms
t4 Programmable delay from EN_T deassertion to VCC_LDO2 Off 6 ms