ZHCS179F August   2011  – July 2016

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Inside the INA826
      2. 8.3.2  Setting the Gain
        1. 8.3.2.1 Gain Drift
      3. 8.3.3  Offset Trimming
      4. 8.3.4  Input Common-Mode Range
      5. 8.3.5  Input Protection
      6. 8.3.6  Input Bias Current Return Path
      7. 8.3.7  Reference Terminal
      8. 8.3.8  Dynamic Performance
      9. 8.3.9  Operating Voltage
        1. 8.3.9.1 Low-Voltage Operation
      10. 8.3.10 Error Sources
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Circuit Breaker
      2. 9.3.2 Programmable Logic Controller (PLC) Input
      3. 9.3.3 Using TINA-TI SPICE-Based Analog Simulation Program with the INA826
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 CMRR vs Frequency
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage –20 20 V
Signal input pins Voltage (–VS) – 40 (+VS) + 40 V
REF pin –20 +20
Output short-circuit(2) Continuous
Temperature Operating, TA –50 150 °C
Junction, TJ 175
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
Machine model (MM) ±150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage Single supply 3 36 V
Dual supply ±1.5 ±18
Specified temperature –40 +125 °C
Operating temperature –50 +150 °C

7.4 Thermal Information

THERMAL METRIC(1) INA826 UNIT
D (SOIC) DGK (VSSOP) DRG (WSON)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 141.4 215.4 50.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 75.4 66.3 60.0 °C/W
RθJB Junction-to-board thermal resistance 59.6 97.8 25.4 °C/W
ψJT Junction-to-top characterization parameter 27.4 10.5 1.2 °C/W
ψJB Junction-to-board characterization parameter 59.1 96.1 25.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a 7.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

7.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOSI Input stage offset voltage(1) RTI 40 150 µV
vs temperature, TA = –40°C to +125°C 0.4 2 µV/°C
VOSO Output stage offset voltage(1) RTI 200 700 µV
vs temperature, TA = –40°C to +125°C 2 10 µV/°C
PSRR Power-supply rejection ratio G = 1, RTI 100 124 dB
G = 10, RTI 115 130
G = 100, RTI 120 140
G = 1000, RTI 120 140
zid Differential impedance 20 || 1 GΩ || pF
zic Common-mode impedance 10 || 5 GΩ || pF
RFI filter, –3-dB frequency 20 MHz
VCM Operating input range(2) V– (V+) – 1 V
VS = ±1.5 V to ±18 V, TA = –40°C to +125°C See Figure 41 to Figure 44
Input overvoltage range TA = –40°C to 125°C ±40 V
CMRR Common-mode rejection ratio At dc to 60 Hz, RTI G = 1, VCM = (V–) to (V+) – 1 V 84 95 dB
G = 10, VCM = (V–) to (V+) – 1 V 104 115
G = 100, VCM = (V–) to (V+) – 1 V 120 130
G = 1000, VCM = (V–) to (V+) – 1 V 120 130
G = 1, VCM = (V–) to (V+) – 1 V,
TA = –40°C to +125°C		 80
At 5 kHz, RTI G = 1, VCM = (V–) to (V+) – 1 V 84
G = 10, VCM = (V–) to (V+) – 1 V 100
G = 100, VCM = (V–) to (V+) – 1 V 105
G = 1000, VCM = (V–) to (V+) – 1 V 105
BIAS CURRENT
IB Input bias current VCM = VS / 2 35 65 nA
TA = –40°C to +125°C 95
IOS Input offset current VCM = VS / 2 0.7 5 nA
TA = –40°C to +125°C 10
NOISE VOLTAGE
eNI Input stage voltage noise(4) f = 1 kHz, G = 100, RS = 0 Ω 18 20 nV/√Hz
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω 0.52 µVPP
eNO Output stage voltage noise(4) f = 1 kHz, G = 1, RS = 0 Ω 110 115 nV/√Hz
fB = 0.1 Hz to 10 Hz, G = 1, RS = 0 Ω 3.3 µVPP
In Noise current f = 1 kHz 100 fA/√Hz
fB = 0.1 Hz to 10 Hz 5 pAPP
GAIN
G Gain equation INA826 q_ec_g_equation_bos562.gif V/V
Range of gain 1 1000 V/V
GE Gain error G = 1, VO = ±10 V ±0.003% ±0.015%
G = 10, VO = ±10 V ±0.03% ±0.15%
G = 100, VO = ±10 V ±0.04% ±0.15%
G = 1000, VO = ±10 V ±0.04% ±0.15%
Gain vs temperature(3) G = 1, TA = –40°C to +125°C ±0.1 ±1 ppm/°C
G > 1, TA = –40°C to +125°C ±10 ±35
Gain nonlinearity G = 1 to 100, VO = –10 V to +10 V 1 5 ppm
G = 1000, VO = –10 V to +10 V 5 20
OUTPUT
Voltage swing RL = 10 kΩ (V–) + 0.1 (V+) – 0.15 V
Load capacitance stability 1000 pF
ZO Open-loop output impedance See Figure 56
ISC Short-circuit current Continuous to VS / 2 ±16 mA
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 1 1 MHz
G = 10 500 kHz
G = 100 60
G = 1000 6
SR Slew rate G = 1, VO = ±14.5 V 1 V/µs
G = 100, VO = ±14.5 V 1
tS Settling time 0.01% G = 1, VSTEP = 10 V 12 µs
G = 10, VSTEP = 10 V 12
G = 100, VSTEP = 10 V 24
G = 1000, VSTEP = 10 V 224
0.001% G = 1, VSTEP = 10 V 14
G = 10, VSTEP = 10 V 14
G = 100, VSTEP = 10 V 31
G = 1000, VSTEP = 10 V 278
REFERENCE INPUT
RIN Input impedance 100 kΩ
Voltage range (V–) (V+) V
Gain to output 1 V/V
Reference gain error 0.01%
POWER SUPPLY
VS Power-supply voltage Single supply 3 36 V
Dual supply ±1.5 ±18
IQ Quiescent current VIN = 0 V 200 250 µA
vs temperature, TA = –40°C to +125°C 250 300
TEMPERATURE RANGE
Specified –40 125 °C
Operating –50 150 °C
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Input voltage range of the INA826 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See Typical Characteristic curves Figure 9 through Figure 16 and Figure 41 through Figure 44 for more information.
(3) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
(4)
Total RTI voltage noise = INA826 q_total_rti_noise_bos562.gif.

7.6 Typical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
INA826 G026_bos562.png
Figure 1. Typical Distribution of Input Offset Voltage
INA826 G025_bos562.png
Figure 3. Typical Distribution of Output Offset Voltage
INA826 G027_bos562.png
Figure 5. Typical Distribution of Input Bias Current
INA826 G052_bos562.png
Figure 7. Typical Gain Error Drift Distribution (G = 1)
INA826 G035_bos562_Rev 1.png
Single supply
Figure 9. Input Common-Mode Voltage vs Output Voltage
INA826 G034_bos562.png
Single supply
Figure 11. Input Common-Mode Voltage vs Output Voltage
INA826 G039_bos562.png
Dual supply
Figure 13. Input Common-Mode Voltage vs Output Voltage
INA826 G040_bos562.png
Dual supply
Figure 15. Input Common-Mode Voltage vs Output Voltage
INA826 G065_bos562.png
G = 1, VS = ±15 V
Figure 17. Input Overvoltage vs Input Current
INA826 G001_bos562.png
Figure 19. CMRR vs Frequency (RTI)
INA826 G003_bos562.png
Figure 21. Positive PSRR vs Frequency (RTI)
INA826 G005_bos562.png
Figure 23. Gain vs Frequency
INA826 G020_bos562.png
Figure 25. Current Noise Spectral Density vs Frequency (RTI)
INA826 G006_bos562.png
Figure 27. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1000)
INA826 G056_bos562.png
VS = 3.0 V
Figure 29. Input Bias Current vs Common-Mode Voltage
INA826 G033_bos562.png
Figure 31. Input Bias Current vs Temperature
INA826 G031_bos562.png
Figure 33. Gain Error vs Temperature (G = 1)
INA826 G032_bos562.png
Figure 35. CMRR vs Temperature (G = 1)
INA826 G021_bos562.png
Figure 37. Gain Nonlinearity (G = 1)
INA826 G023_bos562.png
Figure 39. Gain Nonlinearity (G = 100)
INA826 G057_bos562.png
Figure 41. Offset Voltage vs Negative Common-Mode Voltage
INA826 G059_bos562 Rev2.png
Figure 43. Offset Voltage vs Negative Common-Mode Voltage
INA826 G045_bos562.png
VS = ±15 V
Figure 45. Positive Output Voltage Swing vs Output Current
INA826 G048_bos562.png
Figure 47. Positive Output Voltage Swing vs Output Current
INA826 G014_bos562.png
Figure 49. Large-Signal Frequency Response
INA826 G013_bos562.png
Figure 51. Small-Signal Response Over Capacitive Loads
(G = 1)
INA826 G010_bos562.png
G = 10, RL = 10 kΩ, CL = 100 pF
Figure 53. Small-Signal Response
INA826 G012_bos562.png
G = 1000, RL = 10 kΩ, CL = 100 pF
Figure 55. Small-Signal Response
INA826 G063_bos562.png
Figure 57. Change in Input Offset Voltage vs Warm-Up Time
INA826 G029_bos562.png
Figure 2. Typical Distribution of Input Offset Voltage Drift
INA826 G030_bos562.png
Figure 4. Typical Distribution of Output Offset Voltage Drift
INA826 G028_bos562.png
Figure 6. Typical Distribution of Input Offset Current
INA826 G051_bos562.png
Figure 8. Typical Gain Error Drift Distribution (G > 1)
INA826 G036_bos562 Rev2.png
Single supply
Figure 10. Input Common-Mode Voltage vs Output Voltage
INA826 G037_bos562.png
Single supply
Figure 12. Input Common-Mode Voltage vs Output Voltage
INA826 G038_bos562.png
Dual supply
Figure 14. Input Common-Mode Voltage vs Output Voltage
INA826 G041_bos562.png
Dual supply
Figure 16. Input Common-Mode Voltage vs Output Voltage
INA826 G064_bos562.png
G = 1, VS = ±15 V
Figure 18. Input Overvoltage vs Input Current
with 10-kΩ Resistance
INA826 G002_bos562.png
Figure 20. CMRR vs Frequency
(RTI, 1-kΩ Source Imbalance)
INA826 G004_bos562.png
Figure 22. Negative PSRR vs Frequency (RTI)
INA826 G019_bos562.png
Figure 24. Voltage Noise Spectral Density
vs Frequency (RTI)
INA826 G007_bos562.png
Figure 26. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1)
INA826 G008_bos562.png
Figure 28. 0.1-Hz to 10-Hz RTI Current Noise
INA826 G055_bos562.png
VS = ±15 V
Figure 30. Input Bias Current vs Common-Mode Voltage
INA826 G053_bos562.png
Figure 32. Input Offset Current vs Temperature
INA826 G054_bos562.png
Figure 34. Gain Error vs Temperature (G > 1)
INA826 G043_bos562 Rev 2.png
Figure 36. Supply Current vs Temperature
INA826 G022_bos562.png
Figure 38. Gain Nonlinearity (G = 10)
INA826 G024_bos562.png
Figure 40. Gain Nonlinearity (G = 1000)
INA826 G058_bos562.png
Figure 42. Offset Voltage vs Positive Common-Mode Voltage
INA826 G060_bos562 Rev2.png
Figure 44. Offset Voltage vs Positive Common-Mode Voltage
INA826 G046_bos562.png
VS = ±15 V
Figure 46. Negative Output Voltage Swing vs Output Current
INA826 G049_bos562.png
Figure 48. Negative Output Voltage Swing vs Output Current
INA826 G061_bos562.png
VS = ±15 V
Figure 50. Settling Time vs Step Size
INA826 G009_bos562.png
G = 1, RL = 1 kΩ, CL = 100 pF
Figure 52. Small-Signal Response
INA826 G011_bos562.png
G = 100, RL = 10 kΩ, CL = 100 pF
Figure 54. Small-Signal Response
INA826 G062_bos562.png
Figure 56. Open-Loop Output Impedance