SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The module is configured by the DMA configuration DMABUSCFG register (see Section 13.9.1) and performs single 8-bit or 32-bit nonsequential single transfers by default. Transfer addresses and length parameters of the DMA transfer are byte aligned.
When the AES module requests a DMA transfer, the AHB master asserts and signals to indicate to the arbiter that it requires the bus. This signal stays asserted until the address phase of the last transfer of the DMA and no new DMA transfers are requested.
When no DMA transfers are requested, the AHB master performs IDLE transfers. If the AHB master is already granted and gets the DMA request, the first write transfer is an IDLE transfer. The last transfer is always an IDLE transfer.
If the AHB_MST1_LOCK_EN bit is asserted, the AHB master asserts a lock signal to indicate the AHB is performing a number of indivisible transfers. The arbiter does not grant any other AHB master access to the bus when the first transfer of the sequence of locked transfers has commenced. The AHB master inserts an IDLE transfer after each block sequence.
The AHB master can handle big- and little-endian transfers. The AES module is little-endian oriented internally. However, when connected to a big-endian AHB system, a conversion from big to little endian can be done in the AHB master interface. By default, a little-endian oriented AHB-host system is assumed. When the AHB system is big-endian oriented, the AHB_MST1_BIGEND bit must be set to 1.
The CC13x2x7 and CC26x2x7 device platform does not support burst or non-sequential transfers through internal interconnect. The DMABUSCFG register must not be changed for proper operation.