SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Table 13-15 shows the TAG registers that buffer the TAG from the AES module and can be accessed through DMA or directly with host reads. The TAG registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns zeroes. If an operation does not return a TAG, reading from these registers returns an initialization vector (IV). If an operation returns a TAG plus an IV and both must be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order returns the IV twice.
For a host-read operation, these registers contain the last 128-bit TAG output of the AES core. The TAG is available until the next context is written. This register contains valid data only if the TAG is available, and when the SAVED_CONTEXT_RDY bit in the AESCTL register is set. During processing or for operations and modes that do not return a TAG, reads from this register return data from the IV register.
| AESTAGOUT__0 to AESTAGOUT__3, (Read Only), 32-bit Address Offset: 0x570 to 0x57C in 0x4 byte increments |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AES_TAG[31:0] AES_TAG[63:32] AES_TAG[95:64] AES_TAG[127:96] | |||||||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | Field Name | Description |
|---|---|---|
| 127–0 | TAG | This register contains the authentication TAG for the combined and authentication-only modes. |