SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#TRNG_TRNG_MAP1_TABLE_1 lists the memory-mapped registers for the TRNG registers. All register offset addresses not listed in #TRNG_TRNG_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | OUT0 | Random Number Lower Word Readout Value | #TRNG_TRNG_MAP1_TRNG_ALL_OUT0 |
4h | OUT1 | Random Number Upper Word Readout Value | #TRNG_TRNG_MAP1_TRNG_ALL_OUT1 |
8h | IRQFLAGSTAT | Interrupt Status | #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGSTAT |
Ch | IRQFLAGMASK | Interrupt Mask | #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGMASK |
10h | IRQFLAGCLR | Interrupt Flag Clear | #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGCLR |
14h | CTL | Control | #TRNG_TRNG_MAP1_TRNG_ALL_CTL |
18h | CFG0 | Configuration 0 | #TRNG_TRNG_MAP1_TRNG_ALL_CFG0 |
1Ch | ALARMCNT | Alarm Control | #TRNG_TRNG_MAP1_TRNG_ALL_ALARMCNT |
20h | FROEN | FRO Enable | #TRNG_TRNG_MAP1_TRNG_ALL_FROEN |
24h | FRODETUNE | FRO De-tune Bit | #TRNG_TRNG_MAP1_TRNG_ALL_FRODETUNE |
28h | ALARMMASK | Alarm Event | #TRNG_TRNG_MAP1_TRNG_ALL_ALARMMASK |
2Ch | ALARMSTOP | Alarm Shutdown | #TRNG_TRNG_MAP1_TRNG_ALL_ALARMSTOP |
30h | LFSR0 | LFSR Readout Value | #TRNG_TRNG_MAP1_TRNG_ALL_LFSR0 |
34h | LFSR1 | LFSR Readout Value | #TRNG_TRNG_MAP1_TRNG_ALL_LFSR1 |
38h | LFSR2 | LFSR Readout Value | #TRNG_TRNG_MAP1_TRNG_ALL_LFSR2 |
78h | HWOPT | TRNG Engine Options Information | #TRNG_TRNG_MAP1_TRNG_ALL_HWOPT |
7Ch | HWVER0 | HW Version 0 | #TRNG_TRNG_MAP1_TRNG_ALL_HWVER0 |
1FD8h | IRQSTATMASK | Interrupt Status After Masking | #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTATMASK |
1FE0h | HWVER1 | HW Version 1 | #TRNG_TRNG_MAP1_TRNG_ALL_HWVER1 |
1FECh | IRQSET | Interrupt Set | #TRNG_TRNG_MAP1_TRNG_ALL_IRQSET |
1FF0h | SWRESET | SW Reset Control | #TRNG_TRNG_MAP1_TRNG_ALL_SWRESET |
1FF8h | IRQSTAT | Interrupt Status | #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTAT |
Complex bit access types are encoded to fit into small table cells. #TRNG_TRNG_MAP1_LEGEND shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
OUT0 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_OUT0_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_OUT0_TABLE.
Return to the Summary Table.
Random Number Lower Word Readout Value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE_31_0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VALUE_31_0 | R | 0h | LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. |
OUT1 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_OUT1_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_OUT1_TABLE.
Return to the Summary Table.
Random Number Upper Word Readout Value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE_63_32 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VALUE_63_32 | R | 0h | MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. |
IRQFLAGSTAT is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGSTAT_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGSTAT_TABLE.
Return to the Summary Table.
Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NEED_CLOCK | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHUTDOWN_OVF | RDY | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NEED_CLOCK | R | 0h | 1: Indicates that the TRNG is busy generating entropy
or is in one of its test modes - clocks may not be turned off and
the power supply voltage must be kept stable. 0: TRNG is idle and can be shut down |
30-2 | RESERVED | R | 0h | Reserved |
1 | SHUTDOWN_OVF | R | 0h | 1: The number of FROs shut down (i.e. the number of
'1' bits in the ALARMSTOP register) has exceeded the threshold set
by ALARMCNT.SHUTDOWN_THR Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. |
0 | RDY | R | 0h | 1: Data are available in OUT0 and OUT1. Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to '0'. If a new number is already available in the internal register of the TRNG, the number is directly clocked into the result register. In this case the status bit is asserted again, after one clock cycle. |
IRQFLAGMASK is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGMASK_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGMASK_TABLE.
Return to the Summary Table.
Interrupt Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHUTDOWN_OVF | RDY | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | SHUTDOWN_OVF | R/W | 0h | 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this module. |
0 | RDY | R/W | 0h | 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. |
IRQFLAGCLR is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGCLR_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGCLR_TABLE.
Return to the Summary Table.
Interrupt Flag Clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHUTDOWN_OVF | RDY | |||||
R-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | SHUTDOWN_OVF | W | 0h | 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. |
0 | RDY | W | 0h | 1: Clear IRQFLAGSTAT.RDY. |
CTL is shown in #TRNG_TRNG_MAP1_TRNG_ALL_CTL_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_CTL_TABLE.
Return to the Summary Table.
Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
STARTUP_CYCLES | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
STARTUP_CYCLES | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TRNG_EN | RESERVED | |||||
R-0h | R/W-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NO_LFSR_FB | TEST_MODE | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | STARTUP_CYCLES | R/W | 0h | This field determines the number of samples (between
28 and 224) taken to gather entropy from
the FROs during startup. If the written value of this field is zero,
the number of samples is 224, otherwise the number of
samples equals the written value times 28. 0x0000: 224 samples 0x0001: 1*28 samples 0x0002: 2*28 samples 0x0003: 3*28 samples ... 0x8000: 32768*28 samples 0xC000: 49152*28 samples ... 0xFFFF: 65535*28 samples This field can only be modified while TRNG_EN is 0. If 1 an update will be ignored. |
15-11 | RESERVED | R | 0h | Reserved |
10 | TRNG_EN | R/W | 0h | 0: Forces all TRNG logic back into the idle state
immediately. 1: Starts TRNG, gathering entropy from the FROs for the number of samples determined by STARTUP_CYCLES. |
9-3 | RESERVED | R | 0h | Reserved |
2 | NO_LFSR_FB | R/W | 0h | 1: Remove XNOR feedback from the main LFSR, converting
it into a normal shift register for the XOR-ed outputs of the FROs
(shifting data in on the LSB side). A '1' also forces the LFSR to
sample continuously. This bit can only be set to '1' when TEST_MODE is also set to '1' and should not be used for other than test purposes |
1 | TEST_MODE | R/W | 0h | 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2
registers (the latter are automatically cleared before enabling
access) and keeps IRQFLAGSTAT.NEED_CLOCK at '1'. This bit shall not be used unless you need to change the LFSR seed prior to creating a new random value. All other testing is done external to register control. |
0 | RESERVED | R | 0h | Reserved |
CFG0 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_CFG0_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_CFG0_TABLE.
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Configuration 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MAX_REFILL_CYCLES | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SMPL_DIV | MIN_REFILL_CYCLES | |||||||||||||
R-0h | R/W-0h | R/W-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MAX_REFILL_CYCLES | R/W | 0h | This field determines the maximum number of samples
(between 28 and 224) taken to re-generate
entropy from the FROs after reading out a 64 bits random number. If
the written value of this field is zero, the number of samples is
224, otherwise the number of samples equals the
written value times 28. 0x0000: 224 samples 0x0001: 1*28 samples 0x0002: 2*28 samples 0x0003: 3*28 samples ... 0x8000: 32768*28 samples 0xC000: 49152*28 samples ... 0xFFFF: 65535*28 samples This field can only be modified while CTL.TRNG_EN is 0. |
15-12 | RESERVED | R | 0h | Reserved |
11-8 | SMPL_DIV | R/W | 0h | This field directly controls the number of clock
cycles between samples taken from the FROs. Default value 0
indicates that samples are taken every clock cycle, maximum value 0xF takes one sample every 16 clock cycles. This field must be set to a value such that the slowest FRO (even under worst-case conditions) has a cycle time less than twice the sample period. This field can only be modified while CTL.TRNG_EN is '0'. |
7-0 | MIN_REFILL_CYCLES | R/W | 0h | This field determines the minimum number of samples
(between 26 and 214) taken to re-generate
entropy from the FROs after reading out a 64 bits random number. If
the value of this field is zero, the number of samples is fixed to
the value determined by the MAX_REFILL_CYCLES field, otherwise the
minimum number of samples equals the written value times 64 (which
can be up to 214). To ensure same entropy in all
generated random numbers the value 0 should be used. Then
MAX_REFILL_CYCLES controls the minimum refill interval. The number
of samples defined here cannot be higher than the number defined by
the 'max_refill_cycles' field (i.e. that field takes precedence). No
random value will be created if min refill > max refill. This field can only be modified while CTL.TRNG_EN = 0. 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) 0x01: 1*26 samples 0x02: 2*26 samples ... 0xFF: 255*26 samples |
ALARMCNT is shown in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMCNT_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMCNT_TABLE.
Return to the Summary Table.
Alarm Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | SHUTDOWN_CNT | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SHUTDOWN_THR | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ALARM_THR | |||||||
R/W-FFh | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | 0h | Reserved |
29-24 | SHUTDOWN_CNT | R/W | 0h | Read-only, indicates the number of '1' bits in
ALARMSTOP register. The maximum value equals the number of FROs. |
23-21 | RESERVED | R | 0h | Reserved |
20-16 | SHUTDOWN_THR | R/W | 0h | Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | ALARM_THR | R/W | FFh | Alarm detection threshold for the repeating pattern detectors on each FRO. An FRO 'alarm event' is declared when a repeating pattern (of up to four samples length) is detected continuously for the number of samples defined by this field's value. Reset value 0xFF should keep the number of 'alarm events' to a manageable level. |
FROEN is shown in #TRNG_TRNG_MAP1_TRNG_ALL_FROEN_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_FROEN_TABLE.
Return to the Summary Table.
FRO Enable
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FRO_MASK | ||||||||||||||||||||||||||||||
R-0h | R/W-00FFFFFFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-0 | FRO_MASK | R/W | 00FFFFFFh | Enable bits for the individual FROs. A '1' in bit [n]
enables FRO 'n'. Default state is all '1's to enable all FROs after
power-up. Note that they are not actually started up before the
CTL.TRNG_EN bit is set to '1'. Bits are automatically forced to '0' here (and cannot be written to '1') while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. |
FRODETUNE is shown in #TRNG_TRNG_MAP1_TRNG_ALL_FRODETUNE_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_FRODETUNE_TABLE.
Return to the Summary Table.
FRO De-tune Bit
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FRO_MASK | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-0 | FRO_MASK | R/W | 0h | De-tune bits for the individual FROs. A '1' in bit [n]
lets FRO 'n' run approximately 5% faster. The value of one of these
bits may only be changed while the corresponding FRO is turned off
(by temporarily writing a '0' in the corresponding bit of the FROEN.FRO_MASK register). |
ALARMMASK is shown in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMMASK_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMMASK_TABLE.
Return to the Summary Table.
Alarm Event
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FRO_MASK | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-0 | FRO_MASK | R/W | 0h | Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO 'n' experienced an 'alarm event'. |
ALARMSTOP is shown in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMSTOP_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMSTOP_TABLE.
Return to the Summary Table.
Alarm Shutdown
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FRO_FLAGS | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-0 | FRO_FLAGS | R/W | 0h | Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO 'n' experienced more than one 'alarm event' in quick succession and has been turned off. A '1' in this field forces the corresponding bit in FROEN.FRO_MASK to '0'. |
LFSR0 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR0_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR0_TABLE.
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LFSR Readout Value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LFSR_31_0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LFSR_31_0 | R/W | 0h | Bits [31:0] of the main entropy accumulation LFSR.
Register can only be accessed when CTL.TEST_MODE = 1. Register contents will be cleared to zero before access is enabled. |
LFSR1 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR1_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR1_TABLE.
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LFSR Readout Value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LFSR_63_32 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LFSR_63_32 | R/W | 0h | Bits [63:32] of the main entropy accumulation LFSR.
Register can only be accessed when CTL.TEST_MODE = 1. Register contents will be cleared to zero before access is enabled. |
LFSR2 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR2_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR2_TABLE.
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LFSR Readout Value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LFSR_80_64 | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved |
16-0 | LFSR_80_64 | R/W | 0h | Bits [80:64] of the main entropy accumulation LFSR.
Register can only be accessed when CTL.TEST_MODE = 1. Register contents will be cleared to zero before access is enabled. |
HWOPT is shown in #TRNG_TRNG_MAP1_TRNG_ALL_HWOPT_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_HWOPT_TABLE.
Return to the Summary Table.
TRNG Engine Options Information
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NR_OF_FROS | RESERVED | |||||||||||||
R-0h | R-18h | R-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-6 | NR_OF_FROS | R | 18h | Number of FROs implemented in this TRNG, value 24 (decimal). |
5-0 | RESERVED | R | 0h | Reserved |
HWVER0 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_HWVER0_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_HWVER0_TABLE.
Return to the Summary Table.
HW Version 0
EIP Number And Core Revision
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | HW_MAJOR_VER | HW_MINOR_VER | HW_PATCH_LVL | ||||||||||||
R-0h | R-2h | R-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EIP_NUM_COMPL | EIP_NUM | ||||||||||||||
R-B4h | R-4Bh | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-24 | HW_MAJOR_VER | R | 2h | 4 bits binary encoding of the major hardware revision number. |
23-20 | HW_MINOR_VER | R | 0h | 4 bits binary encoding of the minor hardware revision number. |
19-16 | HW_PATCH_LVL | R | 0h | 4 bits binary encoding of the hardware patch level, initial release will carry value zero. |
15-8 | EIP_NUM_COMPL | R | B4h | Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. |
7-0 | EIP_NUM | R | 4Bh | 8 bits binary encoding of the module number. This TRNG gives 0x4B. |
IRQSTATMASK is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTATMASK_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTATMASK_TABLE.
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Interrupt Status After Masking
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHUTDOWN_OVF | RDY | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | SHUTDOWN_OVF | R | 0h | Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with IRQFLAGMASK.SHUTDOWN_OVF) |
0 | RDY | R | 0h | New random value available (result of IRQFLAGSTAT.RDY AND'ed with IRQFLAGMASK.RDY) |
HWVER1 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_HWVER1_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_HWVER1_TABLE.
Return to the Summary Table.
HW Version 1
TRNG Revision Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REV | ||||||||||||||||||||||||||||||
R-0h | R-20h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | REV | R | 20h | The revision number of this module is Rev 2.0. |
IRQSET is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSET_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSET_TABLE.
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Interrupt Set
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
SWRESET is shown in #TRNG_TRNG_MAP1_TRNG_ALL_SWRESET_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_SWRESET_TABLE.
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SW Reset Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESET | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RESET | R/W | 0h | Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 for reset to be completed. |
IRQSTAT is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTAT_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTAT_TABLE.
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Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | STAT | R | 0h | TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and IRQFLAGSTAT.RDY |