Revisions Affected

0, A

Details

There is a potential temporary internal shunt to V_SS condition identified on pins GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO46, and GPIO47. In this condition, an on-chip path to V_SS is turned on, which can bring down the logic level of these pins below V_IL and V_OL. The condition can occur when the pin is in input or output mode and with any of the alternate functions muxed on to this pin.

The condition is more likely to occur at high temperatures and has not been observed below 85°C under normal operating use cases. The triggering event is dependent on board design and the speed of signals switching on these pins, with fast-switching transients more likely to induce the condition. The condition has only been observed when the signal at the device pin has a rise time or fall time faster than 2 ns (measured 10% to 90% of V_DDIO).

The condition will resolve upon toggle of the IO at a lower temperature.

Workarounds

Try one of these two options:

• Option 1:

  Avoid the use of these pins in the revisions affected.

• Option 2:

  This condition is not seen on all products. Many PCB designs have enough capacitance and slow enough edge rates that the condition does not occur. If the application can be tested and functions correctly with the temperature margin above the end-use temperature, then no action may be required. If the issue is seen or additional margin is desired, then the following can be applied.

  Place a capacitor of 56 pF or greater between each of these pins and ground, placed as closely as possible to the device. This will slow down the fast transient seen by the device and avoid triggering the condition. Larger capacitors will be more effective at filtering the transient but must be balanced against the PCB level timing requirements of these pins.