SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

4.1 Test Setup

Table 6 captures the HIC and EMIF configuration used in the example. The total number of pins required for this configuration is 19.

Table 6. Device and Host Configurations for Pin Constrained Applications

HIC Configuration EMIF Configuration
Access type: Mailbox mode Access Type: Select strobe
Data width: 8-bit mode ASIZE: 8-bit data bus
Read/write: Single pin

Figure 10 shows the hardware connections required for the example. The access type used in this example is mailbox mode and hence the HIC_nRDY and HIC_BASESEL pins are not connected. Also, since the data width mode is set to 8, the byte enables are not required.

spracr2-hardware-setup-for-the-example-hic-ex2-config-8-bit-adc.gifFigure 10. Hardware Setup for the Example hic_ex2_config_8bit_adc